Remove intf_idx and wb_idx fields from struct dpu_encoder_phys and
struct dpu_enc_phys_init_params. Set the hw_intf and hw_wb directly and
use them to get the instance index.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 72 ++
There is no need to assign a result to temp varable just to return it
two lines below. Drop the temporary variable.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/
Move common DPU physical encoder initialization code to the new function
dpu_encoder_phys_init().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 +--
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 3 ++
.../drm/msm/disp/dpu1/dpu_encoder_p
There is no need to assign a result to temp varable just to return it
after a goto. Drop the temporary variable and goto and return the result
directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 10 ++
1 file changed, 2 insertions(+), 8 del
There is little sense to get intf index just to call dpu_rm_get_intf()
on it. Move dpu_rm_get_intf() call to dpu_encoder_get_intf() function.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20
1 file changed, 8 i
The function dpu_encoder_get_wb() returns controller_id if the
corresponding WB is present in the catalog. We can inline this function
and rely on dpu_rm_get_wb() returning NULL for indices for which the
WB is not present on the device.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
Rework dpu_encoder initialization code, simplifying calling sequences
and separating common init parts.
Changes since v1:
- Withdrawn two pathes for a later consideration
- Changed dpu_encoder_phys_init() to return void (Abhinav)
- Added small simplifications of dpu_encoder_phys_cmd_init() and
d
There is no reason to split the dpu_encoder interface into separate
_init() and _setup() phases. Merge them into a single function.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 55 +
drivers/gpu/drm/msm/disp/dpu1/dpu_en
Writeback was the last user of dpu_encoder_phys_ops's atomic_check()
callback. As the code was moved to the dpu_writeback.c, the callback
becomes unused. Drop it now.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 15 ---
drivers/gpu/drm/msm/di
dpu_encoder_phys_wb is the only user of encoder's atomic_check callback.
Move corresponding checks to drm_writeback_connector's implementation
and drop the dpu_encoder_phys_wb_atomic_check() function.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 54
The writeback backend of the dpu_encoder is the only user of the
dpu_encoder_phys_ops::atomic_check() callback. Move corresponding code
to the DPU's drm_writeback_connector implementation (dpu_writeback.c)
and drop corresponding callback code.
Dependency chanin:
- https://patchwork.freedesktop.org
On 19/05/2023 02:46, Abhinav Kumar wrote:
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
Up to now the driver has been using encoder to allocate hardware
resources. Switch it to use CRTC id in preparation for the next step.
This decision to use encoder id instead of CRTC has been there
down
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
Up to now the driver has been using encoder to allocate hardware
resources. Switch it to use CRTC id in preparation for the next step.
This decision to use encoder id instead of CRTC has been there
downstream for quite sometime. So most of the
On 19/05/2023 02:33, Kuogee Hsieh wrote:
Currently DSC flushing happens during interface configuration at
dpu_hw_ctl_intf_cfg_v1(). Separate DSC flush away from
dpu_hw_ctl_intf_cfg_v1() by adding dpu_hw_ctl_update_pending_flush_dsc_v1()
to handle both per-DSC engine and DSC flush bits at same tim
Unset DSC_ACTIVE bit at dpu_hw_ctl_reset_intf_cfg_v1(),
dpu_encoder_unprep_dsc() and dpu_encoder_dsc_pipe_clr() functions
to tear down DSC data path if DSC data path was setup previous.
Changes in V10:
-- pass ctl directly instead of dpu_enc to dsc_pipe_cfg()
-- move both dpu_encoder_unprep_dsc()
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine (DCE) contains
dual DSC encoders so both share same base address but with its own
different sub block address.
changes in v4:
-- delete DPU_DSC_H
There are two tiers of pending flush control, main controller and
individual hardware block. Currently only the main controller of
flush mask is reset to 0 but leave out some individual pending flush
mask of particular hardware block keep previous value at
clear_pending_flush(). Reset all individua
Currently DSC flushing happens during interface configuration at
dpu_hw_ctl_intf_cfg_v1(). Separate DSC flush away from
dpu_hw_ctl_intf_cfg_v1() by adding dpu_hw_ctl_update_pending_flush_dsc_v1()
to handle both per-DSC engine and DSC flush bits at same time to make it
consistent with the location o
Disabling the crossbar mux between DSC and PINGPONG currently
requires a bogus enum dpu_pingpong value to be passed when calling
dsc_bind_pingpong_blk() with enable=false, even though the register
value written is independent of the current PINGPONG block. Replace
that `bool enable` parameter with
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at dpu_hw_dsc_config_1_2()
-- unrolling thresh loops
Changes in v4:
-- delete DPU_DSC_HW_REV_1_1
-- delete
DPU < 7.0.0 requires the PINGPONG block to be involved during
DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC
encoder engine was moved to INTF with the help of the flush mechanism.
Add a DPU_PINGPONG_DSC feature bit to restrict the availability of
dpu_hw_pp_setup_dsc() and dpu_hw_
DPU < 7.0.0 has DPU_PINGPONG_DSC feature bit set to indicate it requires
both dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() to be
executed to complete DSC configuration if DSC hardware block is present.
Hence test DPU_PINGPONG_DSC feature bit and assign DSC related functions
to the ops
From: Abhinav Kumar
Some platforms have DSC blocks which have not been declared in the catalog.
Complete DSC 1.1 support for all platforms by adding the missing blocks to
MSM8998 and SC8180X.
Changes in v9:
-- add MSM8998 and SC8180x to commit titil
Changes in v10:
-- fix grammar at commit text
This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
The DSI and DP parts will be pushed later on top of this change.
This seriel is rebase on [1], [2] and catalog fixes from rev-4 of [3].
[1]: https://patchwork.fr
On 5/17/2023 4:53 PM, Abhinav Kumar wrote:
On 5/14/2023 10:06 AM, Dmitry Baryshkov wrote:
On Sat, 13 May 2023 at 01:39, Abhinav Kumar
wrote:
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
The struct dpu_rm_requirements was used to wrap display topology and
hw resources, which meant INTF i
On 19/05/2023 01:09, Kuogee Hsieh wrote:
On 5/17/2023 3:31 PM, Marijn Suijten wrote:
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -139,6 +139,11 @@ static inline void
dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
Now as the struct dpu_hw_pipe_qos_cfg consists of only one bool field,
drop the structure and use corresponding bool directly.
Reviewed-by: Jeykumar Sankaran
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 10 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ssp
This flag is always passed to _dpu_plane_set_qos_ctrl(), so drop it and
remove corresponding conditions from the mentioned function.
Reviewed-by: Jeykumar Sankaran
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 27 +++
1 file changed, 8 inser
Drop support for DPU_PLANE_QOS_VBLANK_CTRL flag. It is not used both
in upstream driver and in vendor SDE driver.
Reviewed-by: Jeykumar Sankaran
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c| 8
The function dpu_plane_sspp_update_pipe() contains code to skip enabling
the QoS and OT limitis for CURSOR pipes. However all DPU since sdm845
repurpose DMA SSPP for the cursor planes because they lack the real
CURSOR SSPP. Fix the condition to actually check that the plane is
CURSOR or not.
Revie
Rework SSPP and WB code to use common helper for programming QoS
settings.
Reviewed-by: Jeykumar Sankaran
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 31 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_s
Get rid of intermediatory configuration structure and defines. Pass the
format and the enablement bit directly to the new helper. The
WB_CDP_CNTL register ignores BIT(2), so we can write it for both SSPP
and WB CDP settings.
Reviewed-by: Jeykumar Sankaran
Signed-off-by: Dmitry Baryshkov
---
...
After removal of DPU_PLANE_QOS_VBLANK_CTRL, several fields of struct
dpu_hw_pipe_qos_cfg are fixed to false/0. Drop them from the structure
(and drop the corresponding code from the functions).
The DPU_PLANE_QOS_VBLANK_AMORTIZE flag is also removed, since it is now
a NOP.
Reviewed-by: Jeykumar Sa
Slightly rearrainge code in dpu_plane_sspp_update_pipe() to group
QoS/LUT related functions.
Reviewed-by: Jeykumar Sankaran
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/
Reorder SSPP register definitions to sort them in the ascending order.
Move register bitfields after the register definitions.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 64 ++---
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git
Merge SSPP and WB code programming QoS and CDP. This allows us to drop
intermediate structures and duplicate code.
Changes since v2:
- Moved SSPP_VIG_CSC_10_OP_MODE close to other CSC10 defines (Jeykumar)
Changes since v1:
- Fixed kerneldoc for _dpu_plane_set_qos_ctrl()
- Fixed danger_safe_en pro
On 5/18/2023 2:36 PM, Marijn Suijten wrote:
On 2023-05-19 00:26:33, Dmitry Baryshkov wrote:
On 18/05/2023 22:41, Marijn Suijten wrote:
On 2023-04-28 15:36:46, Abhinav Kumar wrote:
Since GC and IGC masks have now been dropped DSPP_MSM8998_MASK
is same as DSPP_SC7180_MASK. Since DSPP_SC7180_M
On 5/17/2023 3:31 PM, Marijn Suijten wrote:
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -139,6 +139,11 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct
dpu_hw_ctl *ctx)
CTL_DSPP_n_FLUSH(dspp - DS
On 19/05/2023 00:39, Marijn Suijten wrote:
On 2023-05-19 00:06:15, Dmitry Baryshkov wrote:
On 18/05/2023 22:14, Marijn Suijten wrote:
On 2023-04-29 04:23:51, Dmitry Baryshkov wrote:
The src_blk declares a lame copy of main SSPP register space. It's
offset is always 0. It's length has been fixe
On 2023-05-19 00:06:15, Dmitry Baryshkov wrote:
> On 18/05/2023 22:14, Marijn Suijten wrote:
> > On 2023-04-29 04:23:51, Dmitry Baryshkov wrote:
> >> The src_blk declares a lame copy of main SSPP register space. It's
> >> offset is always 0. It's length has been fixed to 0x150, while SSPP's
> >
>
On 2023-05-19 00:26:33, Dmitry Baryshkov wrote:
> On 18/05/2023 22:41, Marijn Suijten wrote:
> > On 2023-04-28 15:36:46, Abhinav Kumar wrote:
> >> Since GC and IGC masks have now been dropped DSPP_MSM8998_MASK
> >> is same as DSPP_SC7180_MASK. Since DSPP_SC7180_MASK is used more
> >
> > is *the* s
.len = 0x90, .version = 0x4},
---
base-commit: 798d276b39e984345d52b933a900a71fa0815928
change-id: 20230518-dpu-sc7180-pcc-version-389a2b4ebcb2
Best regards,
--
Marijn Suijten
On 18/05/2023 22:41, Marijn Suijten wrote:
On 2023-04-28 15:36:46, Abhinav Kumar wrote:
Since GC and IGC masks have now been dropped DSPP_MSM8998_MASK
is same as DSPP_SC7180_MASK. Since DSPP_SC7180_MASK is used more
is *the* same
And, I think, a comma is missing before DSPP_MSM8998_MASK.
No
On 19/05/2023 00:06, Marijn Suijten wrote:
On 2023-05-05 23:40:32, Konrad Dybcio wrote:
Add SM6350 support to the DPU1 driver to enable display output.
It's worth noting that one entry dpu_qos_lut_entry was trimmed off:
{.fl = 0, .lut = 0x0011223344556677 },
Is this macrotile-qseed? Not rea
On 21/04/2023 02:05, Konrad Dybcio wrote:
On 21.04.2023 00:41, Dmitry Baryshkov wrote:
On 21/04/2023 01:31, Konrad Dybcio wrote:
Add SM6350 support to the DPU1 driver to enable display output.
Signed-off-by: Konrad Dybcio
Signed-off-by: Konrad Dybcio
---
[...]
+
+static const struct dpu
On 2023-05-05 23:40:32, Konrad Dybcio wrote:
> Add SM6350 support to the DPU1 driver to enable display output.
>
> It's worth noting that one entry dpu_qos_lut_entry was trimmed off:
>
> {.fl = 0, .lut = 0x0011223344556677 },
Is this macrotile-qseed? Not really following where this is supposed
On 18/05/2023 22:14, Marijn Suijten wrote:
On 2023-04-29 04:23:51, Dmitry Baryshkov wrote:
The src_blk declares a lame copy of main SSPP register space. It's
offset is always 0. It's length has been fixed to 0x150, while SSPP's
It's -> its, twice.
Ack
length is now correct. Drop the sr
On 2023-04-30 00:25:12, Dmitry Baryshkov wrote:
> The driver doesn't support hsic/memcolor and pcc SSPP subblocks.
Double space.
(doesn't support, hence the field members are unused allowing us to drop
them.)
> Drop corresponding definitions.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by:
On 2023-04-28 15:36:46, Abhinav Kumar wrote:
> Since GC and IGC masks have now been dropped DSPP_MSM8998_MASK
> is same as DSPP_SC7180_MASK. Since DSPP_SC7180_MASK is used more
is *the* same
> than DSPP_MSM8998_MASK, lets drop the latter.
>
> Signed-off-by: Abhinav Kumar
> Reviewed-by: Dmitry B
On 2023-04-28 15:36:45, Abhinav Kumar wrote:
> Gamma Correction (GC) and Inverse Gamma Correction(IGC) is
> currently unused. In addition dpu_dspp_sub_blks didn't even have an igc
> member describing the block.
>
> Drop related code from the dpu hardware catalog otherwise this becomes a
> burden t
On 2023-04-29 04:23:53, Dmitry Baryshkov wrote:
> Stop using _sspp_subblk_offset() to get offset of the csc_blk. Inline
the offset of.
> this function and use ctx->cap->sblk->csc_blk.base directly.
>
> As this was the last user, drop _sspp_subblk_offset() too.
>
> Reviewed-by: Jeykumar Sankaran
On 2023-04-29 04:23:52, Dmitry Baryshkov wrote:
> Stop using _sspp_subblk_offset() to get offset of the scaler_blk. Inline
the offset of the...
> this function and use ctx->cap->sblk->scaler_blk.base directly.
>
> Reviewed-by: Jeykumar Sankaran
> Signed-off-by: Dmitry Baryshkov
Much cleaner a
On 2023-04-29 04:23:51, Dmitry Baryshkov wrote:
> The src_blk declares a lame copy of main SSPP register space. It's
> offset is always 0. It's length has been fixed to 0x150, while SSPP's
It's -> its, twice.
> length is now correct. Drop the src_blk and access SSPP registers
> without addition
On 5/18/2023 12:05 AM, Marijn Suijten wrote:
On 2023-05-17 16:22:37, Abhinav Kumar wrote:
@@ -529,6 +539,19 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk =
{
.features = _features, \
}
+/*
+ * NOTE: Each display compression engine (DCE) contains dual hard
On Thu, May 18, 2023 at 2:43 AM Tvrtko Ursulin
wrote:
>
>
> In case you were waiting for me looking at the rest of the series, there
> was this reply from the previous round I can expand on.
>
> On 02/05/2023 08:50, Tvrtko Ursulin wrote:
> >
> > On 01/05/2023 17:58, Rob Clark wrote:
> >> On Fri, A
Hi
Am 18.05.23 um 14:46 schrieb Sui Jingfeng:
Hi,
On 2023/5/17 15:07, Thomas Zimmermann wrote:
Hi
Am 17.05.23 um 03:58 schrieb Sui Jingfeng:
Hi, Thomas
After apply your patch set, the kernel with
arch/loongarch/configs/loongson3_defconfig
can not finish compile anymore. gcc complains:
On 2023-05-17 18:14:31, Jessica Zhang wrote:
> Introduce MSM-specific DSC helper methods, as some calculations are
> common between DP and DSC.
>
> Signed-off-by: Jessica Zhang
Reviewed-by: Marijn Suijten
Thanks!
> ---
> drivers/gpu/drm/msm/msm_dsc_helper.h | 38
> ++
In case you were waiting for me looking at the rest of the series, there
was this reply from the previous round I can expand on.
On 02/05/2023 08:50, Tvrtko Ursulin wrote:
On 01/05/2023 17:58, Rob Clark wrote:
On Fri, Apr 28, 2023 at 4:05 AM Tvrtko Ursulin
wrote:
On 27/04/2023 18:53, R
On 2023-05-17 16:22:37, Abhinav Kumar wrote:
> >> @@ -529,6 +539,19 @@ static const struct dpu_pingpong_sub_blks
> >> sc7280_pp_sblk = {
> >>.features = _features, \
> >>}
> >>
> >> +/*
> >> + * NOTE: Each display compression engine (DCE) contains dual hard
> >> + * slice DSC encoders
On 2023-05-18 03:35:31, Dmitry Baryshkov wrote:
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> > index 6292002..d5f3ef8 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
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