Hi Dmitry,
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Dmitry-Baryshkov/drm-msm-another-fix-for-the-headless-Adreno-GPU/20221231-103022
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link:
ht
On 1/4/2023 5:47 PM, Dmitry Baryshkov wrote:
Fix another oops reproducible when rebooting the board with the Adreno
GPU working in the headless mode (e.g. iMX platforms).
Unable to handle kernel NULL pointer dereference at virtual address
when read
[] *pgd=74936831, *pte=000
On Wed, Jan 4, 2023 at 5:47 PM Dmitry Baryshkov
wrote:
>
> Fix another oops reproducible when rebooting the board with the Adreno
> GPU working in the headless mode (e.g. iMX platforms).
>
> Unable to handle kernel NULL pointer dereference at virtual address
> when read
> [] *pgd
On Wed, 04 Jan 2023 10:08:44 +0100, Neil Armstrong wrote:
> Document the MDSS and DPU blocks found on the Qualcomm SM8550
> platform.
>
> Signed-off-by: Neil Armstrong
> ---
> .../bindings/display/msm/qcom,sm8550-dpu.yaml | 134 +
> .../bindings/display/msm/qcom,sm8550-mdss.yaml
On 05/01/2023 01:40, Jessica Zhang wrote:
Initialize and use the color_fill properties for planes in DPU driver. In
addition, relax framebuffer requirements within atomic commit path and
add checks for NULL framebuffers. Finally, drop DPU_PLANE_COLOR_FILL_FLAG
as it's unused.
Changes since V2:
-
On 05/01/2023 01:40, Jessica Zhang wrote:
Add support for solid_fill property to drm_plane. In addition, add
support for setting and getting the values for solid_fill.
solid_fill holds data for supporting solid fill planes. The property
accepts an RGB323232 value and the driver data is formatted
On 05/01/2023 01:40, Jessica Zhang wrote:
Loosen the requirements for atomic and legacy commit so that, in cases
where solid fill planes is enabled (and FB_ID is NULL), the commit can
still go through.
In addition, add framebuffer NULL checks in other areas to account for
FB being NULL when soli
On 05/01/2023 01:40, Jessica Zhang wrote:
Add support for solid_fill property to drm_plane. In addition, add
support for setting and getting the values for solid_fill.
solid_fill holds data for supporting solid fill planes. The property
accepts an RGB323232 value and the driver data is formatted
Fix another oops reproducible when rebooting the board with the Adreno
GPU working in the headless mode (e.g. iMX platforms).
Unable to handle kernel NULL pointer dereference at virtual address
when read
[] *pgd=74936831, *pte=, *ppte=
Internal error: Oops: 17 [#1
Initialize and use the color_fill properties for planes in DPU driver. In
addition, relax framebuffer requirements within atomic commit path and
add checks for NULL framebuffers. Finally, drop DPU_PLANE_COLOR_FILL_FLAG
as it's unused.
Changes since V2:
- Fixed dropped 'const' warning
- Dropped use
Add support for solid_fill property to drm_plane. In addition, add
support for setting and getting the values for solid_fill.
solid_fill holds data for supporting solid fill planes. The property
accepts an RGB323232 value and the driver data is formatted as such:
struct drm_solid_fill {
u
Loosen the requirements for atomic and legacy commit so that, in cases
where solid fill planes is enabled (and FB_ID is NULL), the commit can
still go through.
In addition, add framebuffer NULL checks in other areas to account for
FB being NULL when solid fill is enabled.
Changes in V2:
- Changed
Introduce and add support for a solid_fill property. When the solid_fill
property is set, and the framebuffer is set to NULL, memory fetch will be
disabled.
In addition, loosen the NULL FB checks within the atomic commit callstack
to allow a NULL FB when the solid_fill property is set and add FB c
On 04/01/2023 20:15, Rob Clark wrote:
On Wed, Jan 4, 2023 at 10:09 AM Abhinav Kumar wrote:
On 1/3/2023 7:51 AM, Dmitry Baryshkov wrote:
Fix another oops reproducible when rebooting the board with the Adreno
GPU wokring in the headless mode (e.g. iMX platforms).
wokring ---> working
Unabl
On Wed, Jan 4, 2023 at 10:09 AM Abhinav Kumar wrote:
>
>
>
> On 1/3/2023 7:51 AM, Dmitry Baryshkov wrote:
> > Fix another oops reproducible when rebooting the board with the Adreno
> > GPU wokring in the headless mode (e.g. iMX platforms).
> wokring ---> working
> >
> > Unable to handle kernel NUL
On 1/3/2023 7:51 AM, Dmitry Baryshkov wrote:
Fix another oops reproducible when rebooting the board with the Adreno
GPU wokring in the headless mode (e.g. iMX platforms).
wokring ---> working
Unable to handle kernel NULL pointer dereference at virtual address
when read
[]
On Wed, 4 Jan 2023 at 12:08, Neil Armstrong wrote:
>
> On 04/01/2023 10:45, Dmitry Baryshkov wrote:
> > On 04/01/2023 11:08, Neil Armstrong wrote:
> >> Add definitions for the display hardware used on Qualcomm SM8550
> >> platform.
> >>
> >> Signed-off-by: Neil Armstrong
> >> ---
> >> drivers/g
On Wed, 4 Jan 2023 at 12:11, Neil Armstrong wrote:
>
> On 04/01/2023 10:53, Dmitry Baryshkov wrote:
> > On 04/01/2023 11:08, Neil Armstrong wrote:
> >> SM8550 use a 4nm DSI PHYs, which share register definitions
> >> with 7nm DSI PHYs. Rather than duplicating the driver, handle
> >> 4nm variant in
On 04/01/2023 10:53, Dmitry Baryshkov wrote:
On 04/01/2023 11:08, Neil Armstrong wrote:
SM8550 use a 4nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle
4nm variant inside the common 5+7nm driver.
Signed-off-by: Neil Armstrong
---
driv
On 04/01/2023 10:45, Dmitry Baryshkov wrote:
On 04/01/2023 11:08, Neil Armstrong wrote:
Add definitions for the display hardware used on Qualcomm SM8550
platform.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 +
drivers/gpu/dr
On 04/01/2023 11:08, Neil Armstrong wrote:
Add support for DSI 2.7.0 (block used on sm8550).
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 16
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 17 insertions(+)
Reviewed-by: Dmitry Baryshko
On 04/01/2023 11:08, Neil Armstrong wrote:
SM8550 use a 4nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle
4nm variant inside the common 5+7nm driver.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/Kconfig | 4 +-
On 04/01/2023 11:08, Neil Armstrong wrote:
Add support for the MDSS block on SM8550 platform.
Signed-off-by: Neil Armstrong
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu
On 04/01/2023 11:08, Neil Armstrong wrote:
Add definitions for the display hardware used on Qualcomm SM8550
platform.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
dri
On 04/01/2023 02:29, Rob Herring wrote:
On Fri, Dec 23, 2022 at 02:10:14AM +, Bryan O'Donoghue wrote:
Add the list of current compats absent the deprecated qcm2290 to the list
of dsi compats listed here.
Several MDSS yaml files exist which document the dsi sub-node.
For each existing SoC MD
SM8550 use a 4nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle
4nm variant inside the common 5+7nm driver.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/Kconfig | 4 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c |
Add support for DSI 2.7.0 (block used on sm8550).
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 16
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
b/drivers/gpu/drm/msm/dsi/dsi_
Add support for the MDSS block on SM8550 platform.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/msm_mdss.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 144c8dd82be1..54483fe30ffd 100644
--- a/drivers/gpu/drm/
Add definitions for the display hardware used on Qualcomm SM8550
platform.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|
Document the MDSS and DPU blocks found on the Qualcomm SM8550
platform.
Signed-off-by: Neil Armstrong
---
.../bindings/display/msm/qcom,sm8550-dpu.yaml | 134 +
.../bindings/display/msm/qcom,sm8550-mdss.yaml | 331 +
2 files changed, 465 insertions(+)
diff -
Document the SM8550 DSI PHY which is very close from the 7nm
and 5nm DSI PHYs found in earlier platforms.
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display
This adds support for the MDSS/DPU/DSI on the Qualcomm SM8550 platform.
This patchset is based on the SM8450 display support serie at [1].
In order to work, the following patchsets are required:
- PM8550 LDO fix at [2]
- DISPCC driver at [3]
+ the DT changes.
[1]
https://lore.kernel.org/all/20
On 04/01/2023 08:29, Tomi Valkeinen wrote:
On 28/12/2022 23:58, Dmitry Baryshkov wrote:
On 02/11/2022 20:06, Dmitry Baryshkov wrote:
From all the drivers using drm_bridge_connector only iMX/dcss and OMAP
DRM driver do a proper work of calling
drm_bridge_connector_en/disable_hpd() in right plac
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