Because of the possilble failure of devm_kzalloc(), dpu_wb_conn might
be NULL and will cause null pointer derefrence later.
Therefore, it might be better to check it and directly return -ENOMEM.
Fixes: 77b001acdcfe ("drm/msm/dpu: add the writeback connector layer")
Signed-off-by: Hui Tang
---
d
On 10/25/2022 8:26 PM, Bjorn Andersson wrote:
From: Bjorn Andersson
Define the display clock controllers, the MDSS instances, the DP phys
and connect these together.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v2:
- New patch on list
arch/arm64/boot/
On 11/11/2022 1:45 AM, Daniel Vetter wrote:
On Wed, Nov 09, 2022 at 05:44:37PM -0800, Jessica Zhang wrote:
On 11/9/2022 5:59 AM, Daniel Vetter wrote:
On Wed, Nov 09, 2022 at 04:53:45PM +0300, Dmitry Baryshkov wrote:
On 09/11/2022 16:52, Daniel Vetter wrote:
On Tue, Nov 08, 2022 at 06:25:
On 18/11/2022 18:36, Kuogee Hsieh wrote:
Add DP both data-lanes and link-frequencies property to dp_out endpoint and
support
functions to DP driver.
Kuogee Hsieh (2):
arm64: dts: qcom: add data-lanes and link-freuencies into dp_out
endpoint
drm/msm/dp: add support of max dp link rate
dp_out endpoint contains both data-lanes and link-frequencies properties.
This patch parser dp_out endpoint properties and acquire dp_max_lanes and
dp_max_link_rate from respective property. Finally, comparing them against
both data lane and link rate read back from sink to ensure both data lane
an
Add DP both data-lanes and link-frequencies property to dp_out endpoint and
support
functions to DP driver.
Kuogee Hsieh (2):
arm64: dts: qcom: add data-lanes and link-freuencies into dp_out
endpoint
drm/msm/dp: add support of max dp link rate
arch/arm64/boot/dts/qcom/sc7180-trogdor.dts
Add both data-lanes and link-frequencies property to dp_out endpoint.
Also set link-frequencies to 81 khz at herobrine platform to have
max link rate limited at 81 khz (HBR3).
Signed-off-by: Kuogee Hsieh
---
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 9 -
arch/arm64/boot/d
On 18/11/2022 16:37, Kalyan Thota wrote:
-Original Message-
From: Dmitry Baryshkov
Sent: Friday, November 18, 2022 6:09 PM
To: Kalyan Thota (QUIC) ; dri-
de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
freedreno@lists.freedesktop.org; devicet...@vger.kernel.org
Cc: linux-k
On 11/18/2022 5:03 AM, Dan Carpenter wrote:
This code was recently refactored in commit and now the "hdmi" pointer
can't be NULL. Checking for NULL leads to a Smatch warning:
drivers/gpu/drm/msm/hdmi/hdmi.c:141 msm_hdmi_init()
warn: variable dereferenced before check 'hdmi' (see li
>-Original Message-
>From: Dmitry Baryshkov
>Sent: Friday, November 18, 2022 6:09 PM
>To: Kalyan Thota (QUIC) ; dri-
>de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>freedreno@lists.freedesktop.org; devicet...@vger.kernel.org
>Cc: linux-ker...@vger.kernel.org; robdcl...@chro
On 18/11/2022 15:29, Bryan O'Donoghue wrote:
On 08/11/2022 12:46, Dmitry Baryshkov wrote:
On 08/11/2022 02:56, Bryan O'Donoghue wrote:
Currently we do not differentiate between the various users of the
qcom,mdss-dsi-ctrl. The driver is flexible enough to operate from one
compatible string but,
On Fri, Nov 18, 2022 at 01:41:24PM +0100, Krzysztof Kozlowski wrote:
> On 14/11/2022 18:06, Dmitry Baryshkov wrote:
> > The main goal of this patchset is to define a generic qcom,smmu-500
> > binding to be used by newer Qualcomm platforms instead of defining each
> > and every SoC line with no actu
On 08/11/2022 12:46, Dmitry Baryshkov wrote:
On 08/11/2022 02:56, Bryan O'Donoghue wrote:
Currently we do not differentiate between the various users of the
qcom,mdss-dsi-ctrl. The driver is flexible enough to operate from one
compatible string but, the hardware does have some significant
diffe
This code was recently refactored in commit and now the "hdmi" pointer
can't be NULL. Checking for NULL leads to a Smatch warning:
drivers/gpu/drm/msm/hdmi/hdmi.c:141 msm_hdmi_init()
warn: variable dereferenced before check 'hdmi' (see line 119)
Fixes: 69a88d8633ec ("drm/msm/hdmi: move r
On 14/11/2022 18:06, Dmitry Baryshkov wrote:
> Cheza fw does not properly program the GPU aperture to allow the
> GPU to update the SMMU pagetables for context switches. The board file
> works around this by dropping the "qcom,adreno-smmu" compat string.
> Add this usecase to arm,smmu.yaml schema.
On 14/11/2022 18:06, Dmitry Baryshkov wrote:
> The main goal of this patchset is to define a generic qcom,smmu-500
> binding to be used by newer Qualcomm platforms instead of defining each
> and every SoC line with no actual differences between the compats.
>
> While preparing this change it was r
On 18/11/2022 15:16, Kalyan Thota wrote:
Add color management support for the crtc provided there are
enough dspps that can be allocated from the catalog.
Changes in v1:
- cache color enabled state in the dpu crtc obj (Dmitry)
- simplify dspp allocation while creating crtc (Dmitry)
- register fo
On 18/11/2022 15:16, Kalyan Thota wrote:
Since DRM encoder type for few encoders can be similar
(like eDP and DP) find out if the interface supports HPD
from encoder bridge to differentiate between builtin
and pluggable displays.
Changes in v1:
- add connector type in the disp_info (Dmitry)
- ad
On 18/11/2022 15:16, Kalyan Thota wrote:
Pin each crtc with one encoder. This arrangement will
disallow crtc switching between encoders and also will
facilitate to advertise certain features on crtc based
on encoder type.
Changes in v1:
- use drm_for_each_encoder macro while iterating through
Since DRM encoder type for few encoders can be similar
(like eDP and DP) find out if the interface supports HPD
from encoder bridge to differentiate between builtin
and pluggable displays.
Changes in v1:
- add connector type in the disp_info (Dmitry)
- add helper functions to know encoder type
- u
Add color management support for the crtc provided there are
enough dspps that can be allocated from the catalog
Kalyan Thota (3):
drm/msm/disp/dpu1: pin 1 crtc to 1 encoder
drm/msm/disp/dpu1: add helper to know if display is builtin
drm/msm/disp/dpu1: add color management support for the cr
Add color management support for the crtc provided there are
enough dspps that can be allocated from the catalog.
Changes in v1:
- cache color enabled state in the dpu crtc obj (Dmitry)
- simplify dspp allocation while creating crtc (Dmitry)
- register for color when crtc is created (Dmitry)
Chan
Pin each crtc with one encoder. This arrangement will
disallow crtc switching between encoders and also will
facilitate to advertise certain features on crtc based
on encoder type.
Changes in v1:
- use drm_for_each_encoder macro while iterating through
encoder list (Dmitry)
Changes in v2:
- mak
On 18/11/2022 01:49, Kuogee Hsieh wrote:
dp_out endpoint contains both data-lanes and link-frequencies properties.
This patch parser dp_out endpoint properties and acquire dp_max_lanes and
dp_max_link_rate from respective property. Finally, comparing them against
both data lane and link rate read
On Fri, 18 Nov 2022 at 00:50, Kuogee Hsieh wrote:
>
> Add both data-lanes and link-frequencies property to dp_out endpoint.
Bindings update?
Deprecate the old data-lanes property?
> Also set link-frequencies to 81 khz at herobrine platform to have
> max link rate limited at 81 khz (HBR3)
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