This is an SMMU for the adreno gpu, and adding this compatible lets
the driver use per-fd page tables, which are required for security
between GPU clients.
Signed-off-by: Emma Anholt
---
Tested with a full deqp-vk run on RB5, which did involve some iommu faults.
arch/arm64/boot/dts/qcom/sm8250
Required for turning on per-process page tables for the GPU.
Signed-off-by: Emma Anholt
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index d8e1ef83c01b.
On 6/14/2022 2:59 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-06-14 14:05:02)
Display resolution change is implemented through drm modeset. Older
modeset (resolution) has to be disabled first before newer modeset
(resolution) can be enabled. Display disable will turn off both
pixel cloc
On 6/14/2022 2:59 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-06-14 14:05:02)
Display resolution change is implemented through drm modeset. Older
modeset (resolution) has to be disabled first before newer modeset
(resolution) can be enabled. Display disable will turn off both
pixel cloc
Quoting Kuogee Hsieh (2022-06-14 14:05:02)
> Display resolution change is implemented through drm modeset. Older
> modeset (resolution) has to be disabled first before newer modeset
> (resolution) can be enabled. Display disable will turn off both
> pixel clock and main link clock so that main link
Refactor existing CRC code for layer mixer and add CRC support for interface
blocks
Changes since V1:
- Create helper methods for collect_misr and setup_misr in dpu_hw_util.c
- Move common bitmasks into dpu_hw_util.h
- Update copyrights
- Create a dynamically allocated crcs array in dpu_crtc_stat
Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
helper method. This way, we can make it easier to get CRCs from other HW
blocks by adding other get_crc helper methods.
Changes since V1:
- Moved common bitmasks to dpu_hw_util.h
- Moved common CRC methods to dpu_hw_util.c
- U
Add support for writing CRC values for the interface block to
the debugfs by calling the necessary MISR setup/collect methods.
Changes since V1:
- Set values_cnt to only include phys with backing hw_intf
- Loop over all drm_encs connected to crtc
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm
Add support for setting MISR registers within the interface
Changes since V1:
- Replaced dpu_hw_intf collect_misr and setup_misr implementations with
calls to dpu_hw_utils helper methods
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 19 ++-
dri
Display resolution change is implemented through drm modeset. Older
modeset (resolution) has to be disabled first before newer modeset
(resolution) can be enabled. Display disable will turn off both
pixel clock and main link clock so that main link have to be
re-trained during display enable to hav
From: Vladimir Lypak
Add the MDSS, MDP and DSI nodes that are found on msm8953 SoC.
Signed-off-by: Vladimir Lypak
Signed-off-by: Luca Weiss
---
Changes from v1:
- disable nodes by default, thanks Dmitry!
- enable iommu for mdp
arch/arm64/boot/dts/qcom/msm8953.dtsi | 208 +
From: Vladimir Lypak
Add the nodes describing the iommu and its context banks that are found
on msm8953 SoCs.
Signed-off-by: Vladimir Lypak
Signed-off-by: Luca Weiss
---
Changes from v1:
- new patch
arch/arm64/boot/dts/qcom/msm8953.dtsi | 36 +++
1 file changed, 36 in
Document the compatible used for IOMMU on the msm8953 SoC.
Signed-off-by: Luca Weiss
---
Changes from v1:
- new patch
Documentation/devicetree/bindings/iommu/qcom,iommu.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
b/Documentatio
On 6/14/2022 1:38 AM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-06-13 14:48:37)
During display resolution changes display have to be disabled first
followed by display enabling with new resolution. Display disable
will turn off both pixel clock and main link clock so that main link
have t
Remove the hard-coded limit for writeback and lets start using
the one from catalog instead.
Fixes: d7d0e73f7de3 ("introduce the dpu_encoder_phys_* for writeback")
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 6 ++
1 file changed, 2 insertions(+), 4
Writeback block for sm8250 was using the default maxlinewidth
of 2048. But this is not right as it supports upto 4096.
This should have no effect on most resolutions as we are
still limiting upto maxlinewidth of SSPP for adding the modes.
Fix the maxlinewidth for writeback block on sm8250.
Fixes
intf and wb resources are not dependent on the rm global
state so need not be allocated during dpu_encoder_virt_atomic_mode_set().
Move the allocation of intf and wb resources to dpu_encoder_setup_display()
so that we can utilize the hw caps even during atomic_check() phase.
Since dpu_encoder_set
On 6/14/2022 3:09 AM, Dmitry Baryshkov wrote:
On 14/06/2022 13:07, Miaoqian Lin wrote:
Hi, Abhinav
On 2022/6/11 7:20, Abhinav Kumar wrote:
On 6/7/2022 4:08 AM, Miaoqian Lin wrote:
of_graph_get_remote_node() returns remote device node pointer with
refcount incremented, we should use of_no
On Mon, 13 Jun 2022 at 23:49, Rob Clark wrote:
>
> From: Rob Clark
>
> Misc small cleanup I noticed. Not called from another object file since
> 3c9edd9c85f5 ("drm/msm: Introduce GEM object funcs")
>
> Signed-off-by: Rob Clark
Reviewed-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/msm_ge
On 6/14/2022 1:38 AM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2022-06-13 14:48:37)
During display resolution changes display have to be disabled first
followed by display enabling with new resolution. Display disable
will turn off both pixel clock and main link clock so that main link
have t
>From testing on sc7180-trogdor devices, reading the GMU registers
needs the GMU clocks to be enabled. Those clocks get turned on in
a6xx_gmu_resume(). Confusingly enough, that function is called as a
result of the runtime_pm of the GPU "struct device", not the GMU
"struct device". Unfortunately th
Hi,
On Tue, Jun 14, 2022 at 7:42 AM Akhil P Oommen wrote:
>
> On 6/10/2022 5:39 AM, Douglas Anderson wrote:
> > >From testing on sc7180-trogdor devices, reading the GMU registers
> > needs the GMU clocks to be enabled. Those clocks get turned on in
> > a6xx_gmu_resume(). Confusingly enough, that
On 6/10/2022 5:39 AM, Douglas Anderson wrote:
>From testing on sc7180-trogdor devices, reading the GMU registers
needs the GMU clocks to be enabled. Those clocks get turned on in
a6xx_gmu_resume(). Confusingly enough, that function is called as a
result of the runtime_pm of the GPU "struct device
On 14/06/2022 13:07, Miaoqian Lin wrote:
Hi, Abhinav
On 2022/6/11 7:20, Abhinav Kumar wrote:
On 6/7/2022 4:08 AM, Miaoqian Lin wrote:
of_graph_get_remote_node() returns remote device node pointer with
refcount incremented, we should use of_node_put() on it
when not need anymore.
Add missing
Hi, Abhinav
On 2022/6/11 7:20, Abhinav Kumar wrote:
>
>
> On 6/7/2022 4:08 AM, Miaoqian Lin wrote:
>> of_graph_get_remote_node() returns remote device node pointer with
>> refcount incremented, we should use of_node_put() on it
>> when not need anymore.
>> Add missing of_node_put() to avoid refcou
Quoting Kuogee Hsieh (2022-06-13 14:48:37)
> During display resolution changes display have to be disabled first
> followed by display enabling with new resolution. Display disable
> will turn off both pixel clock and main link clock so that main link
> have to be re-trained during display enable t
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