According to the downstram DT file, the qusb2phy ref clock should be
GCC_RX0_USB2_CLKREF_CLK, not GCC_RX1_USB2_CLKREF_CLK.
Fixes: c65a4ed2ea8b ("arm64: dts: qcom: sdm630: Add USB configuration")
Cc: Konrad Dybcio
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dt
Add binding documentation for the Inforce IFC6560 board which uses
Snapdragon SDA660.
Signed-off-by: Dmitry Baryshkov
---
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml
b/Documentation/dev
The SoC's device tree file disables gpucc and adreno's SMMU by default.
So let's disable the GPU too. Moreover it looks like SMMU might be not
usable without additional patches (which means that GPU is unusable
too). No board uses GPU at this moment.
Fixes: 5cf69dcbec8b ("arm64: dts: qcom: sdm630:
Add DT entries for the second DWC3 USB host, which is limited to the
USB2.0 (HighSpeed), and the corresponding QUSB PHY.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sdm630.dtsi | 55
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/
The IFC6560 is a board from Inforce Computing, built around the SDA660
SoC. This patch describes core clocks, some regulators from the two
PMICs, debug uart, storage, bluetooth and audio DSP remoteproc.
The regulator settings are inherited from prior work by Konrad Dybcio
and AngeloGioacchino Del
Replace numeric values with the symbolic names defined in the bindings
header.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sdm630.dtsi | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi
b/arch/arm64
Follow the typical practice and keep DSI1/DSI1 PHY disabled by default.
They should be enabled in the board DT files. No existing boards use
them at this moment.
Reviewed-by: Marijn Suijten
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sdm660.dtsi | 3
Follow the typical practice and keep DSI0/DSI0 PHY disabled by default.
They should be enabled in the board DT files. No existing boards use
them at this moment.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/a
This work is largely based on the previous work by Bjorn Andersson ([1])
Changes since v1 (mostly based on Kondrad's review):
- Also disabled dsi0/dsi0 phy in sdm630.dtsi
- Removed the clock from BAM DMA devices rather than disabling them
completely
- Replaced numbers with symbolic names for int
Hi,
On 5/12/2022 3:44 PM, Doug Anderson wrote:
Hi,
On Thu, May 12, 2022 at 3:34 PM Abhinav Kumar wrote:
On 5/12/2022 3:16 PM, Dmitry Baryshkov wrote:
On 13/05/2022 01:00, Douglas Anderson wrote:
Commit 7d8e9a90509f ("drm/msm/dsi: move DSI host powerup to modeset
time") caused sc7180 Chrome
On 5/6/2022 6:00 PM, Dmitry Baryshkov wrote:
Afther the commit f026e431cf86 ("drm/msm: Convert to Linux IRQ
interfaces") converted MSM DRM driver to handle IRQs on it's own (rather
than using the DRM IRQ mid-layer), there is little point in keeping
irq wrapper in the msm_drv.c which just call
Hi,
On Thu, May 12, 2022 at 3:34 PM Abhinav Kumar wrote:
>
> On 5/12/2022 3:16 PM, Dmitry Baryshkov wrote:
> > On 13/05/2022 01:00, Douglas Anderson wrote:
> >> Commit 7d8e9a90509f ("drm/msm/dsi: move DSI host powerup to modeset
> >> time") caused sc7180 Chromebooks that use the parade-ps8640 bri
On 5/12/2022 3:16 PM, Dmitry Baryshkov wrote:
On 13/05/2022 01:00, Douglas Anderson wrote:
Commit 7d8e9a90509f ("drm/msm/dsi: move DSI host powerup to modeset
time") caused sc7180 Chromebooks that use the parade-ps8640 bridge
chip to fail to turn the display back on after it turns off.
Unfor
On 13/05/2022 01:00, Douglas Anderson wrote:
Commit 7d8e9a90509f ("drm/msm/dsi: move DSI host powerup to modeset
time") caused sc7180 Chromebooks that use the parade-ps8640 bridge
chip to fail to turn the display back on after it turns off.
Unfortunately, it doesn't look easy to fix the parade-p
Hi,
On Thu, May 12, 2022 at 1:59 PM Dmitry Baryshkov
wrote:
>
> On 12/05/2022 23:52, Douglas Anderson wrote:
> > Commit 7d8e9a90509f ("drm/msm/dsi: move DSI host powerup to modeset
> > time") caused sc7180 Chromebooks that use the parade-ps8640 bridge
> > chip to fail to turn the display back on
Commit 7d8e9a90509f ("drm/msm/dsi: move DSI host powerup to modeset
time") caused sc7180 Chromebooks that use the parade-ps8640 bridge
chip to fail to turn the display back on after it turns off.
Unfortunately, it doesn't look easy to fix the parade-ps8640 driver to
handle the new power sequence.
On 12/05/2022 23:52, Douglas Anderson wrote:
Commit 7d8e9a90509f ("drm/msm/dsi: move DSI host powerup to modeset
time") caused sc7180 Chromebooks that use the parade-ps8640 bridge
chip to fail to turn the display back on after it turns off.
Unfortunately, it doesn't look easy to fix the parade-p
Commit 7d8e9a90509f ("drm/msm/dsi: move DSI host powerup to modeset
time") caused sc7180 Chromebooks that use the parade-ps8640 bridge
chip to fail to turn the display back on after it turns off.
Unfortunately, it doesn't look easy to fix the parade-ps8640 driver to
handle the new power sequence.
dp_catalog_ctrl_reset() will software reset DP controller. But it will
not reset programmable registers to default value. DP driver still have
to clear mask bits to interrupt status registers to disable interrupts
after software reset of controller.
At current implementation, dp_ctrl_reset_irq_ctr
On 5/11/2022 6:03 PM, Dmitry Baryshkov wrote:
On Thu, 12 May 2022 at 04:01, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2022-05-11 17:41:50)
On 12/05/2022 03:02, Kuogee Hsieh wrote:
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index af7a80c..f3e333e 100
On 5/11/2022 6:03 PM, Dmitry Baryshkov wrote:
On Thu, 12 May 2022 at 04:01, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2022-05-11 17:41:50)
On 12/05/2022 03:02, Kuogee Hsieh wrote:
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index af7a80c..f3e333e 100
On Thu, May 12, 2022 at 03:28:16PM +0200, Tomeu Vizoso wrote:
> On 5/11/22 7:46 PM, Rob Clark wrote:
> > On Wed, May 11, 2022 at 10:12 AM Daniel Vetter wrote:
> > >
> > > On Tue, 10 May 2022 at 22:26, Rob Clark wrote:
> > > >
> > > > On Tue, May 10, 2022 at 12:39 PM Jessica Zhang
> > > > wrote
On 5/12/2022 5:49 PM, Miaoqian Lin wrote:
of_parse_phandle() returns a node pointer with refcount
incremented, we should use of_node_put() on it when not need anymore.
a6xx_gmu_init() passes the node to of_find_device_by_node()
and of_dma_configure(), of_find_device_by_node() will takes its
refe
On 5/11/22 7:46 PM, Rob Clark wrote:
On Wed, May 11, 2022 at 10:12 AM Daniel Vetter wrote:
On Tue, 10 May 2022 at 22:26, Rob Clark wrote:
On Tue, May 10, 2022 at 12:39 PM Jessica Zhang
wrote:
On 5/10/2022 7:13 AM, Tomeu Vizoso wrote:
And use it to store expectations about what the drm
of_parse_phandle() returns a node pointer with refcount
incremented, we should use of_node_put() on it when not need anymore.
a6xx_gmu_init() passes the node to of_find_device_by_node()
and of_dma_configure(), of_find_device_by_node() will takes its
reference, of_dma_configure() doesn't need the n
On 29/04/2022 21:51, Dmitry Baryshkov wrote:
From all the drivers using drm_bridge_connector only iMX/dcss and OMAP
DRM driver do a proper work of calling
drm_bridge_connector_en/disable_hpd() in right places. Rather than
teaching each and every driver how to properly handle
drm_bridge_connector
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