On Mon, 4 Apr 2022 at 21:21, Sankeerth Billakanti (QUIC)
wrote:
>
> Hi Doug,
>
> > On Wed, Mar 30, 2022 at 11:02 PM Sankeerth Billakanti (QUIC)
> > wrote:
> > >
> > > Hi Dmitry,
> > >
> > > > On Wed, 30 Mar 2022 at 19:04, Sankeerth Billakanti
> > > > wrote:
> > > > >
> > > > > The panel-edp driv
On Mon, 4 Apr 2022 at 21:32, Sankeerth Billakanti (QUIC)
wrote:
>
> Hi Doug,
>
> > On Wed, Mar 30, 2022 at 9:04 AM Sankeerth Billakanti
> > wrote:
> > >
> > > Some eDP sinks or platform boards will not support hpd.
> > > This patch adds support for those cases.
> >
> > You could say more, like:
>
On Mon, 4 Apr 2022 at 16:53, Sankeerth Billakanti (QUIC)
wrote:
>
> Hi Doug,
>
> > On Wed, Mar 30, 2022 at 9:04 AM Sankeerth Billakanti
> > wrote:
> > >
> > > Remove the unnecessary delay in executing the EV_HPD_INIT_SETUP
> > event.
> >
> > Tell me more and put it in the commit message! Why did
Hi,
On Sat, Apr 2, 2022 at 1:26 PM Dmitry Baryshkov
wrote:
>
> On Sat, 2 Apr 2022 at 20:06, Doug Anderson wrote:
> >
> > Hi,
> >
> > On Sat, Apr 2, 2022 at 3:37 AM Dmitry Baryshkov
> > wrote:
> > >
> > > On 01/04/2022 02:22, Doug Anderson wrote:
> > > > Hi,
> > > >
> > > > On Wed, Mar 30, 2022
On Fri, Apr 1, 2022 at 8:38 AM Laurent Pinchart
wrote:
>
> Hi Abhinav,
>
> Thank you for the patch.
>
> On Thu, Mar 31, 2022 at 05:12:13PM -0700, Abhinav Kumar wrote:
> > For some vendor driver implementations, display hardware can
> > be shared between the encoder used for writeback and the physi
Hi Doug,
> On Wed, Mar 30, 2022 at 9:04 AM Sankeerth Billakanti
> wrote:
> >
> > Some eDP sinks or platform boards will not support hpd.
> > This patch adds support for those cases.
>
> You could say more, like:
>
> If we're not using HPD then _both_ the panel node and the eDP controller
> node
Hi Doug,
> On Wed, Mar 30, 2022 at 11:02 PM Sankeerth Billakanti (QUIC)
> wrote:
> >
> > Hi Dmitry,
> >
> > > On Wed, 30 Mar 2022 at 19:04, Sankeerth Billakanti
> > > wrote:
> > > >
> > > > The panel-edp driver modes needs to be validated differently from
> > > > DP because the link capabilities
> On Thu, 31 Mar 2022 at 14:05, Sankeerth Billakanti
> wrote:
> >
> > Hi Dmitry,
> >
> > > On 31/03/2022 08:53, Sankeerth Billakanti (QUIC) wrote:
> > > > Hi Dmitry,
> > > >
> > > >> On Wed, 30 Mar 2022 at 19:03, Sankeerth Billakanti
> > > >> wrote:
> > > >>>
> > > >>> The interrupt register will
On 3/30/2022 3:30 PM, Dmitry Baryshkov wrote:
Make dp_connector_mode_valid() return precise MODE_CLOCK_HIGH rather
than generic MODE_BAD in case the mode clock is higher than
DP_MAX_PIXEL_CLK_KHZ (675 MHz).
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Kuogee Hsieh
drivers/gpu/drm/ms
When DSC is enabled, we need to configure DSI registers accordingly and
configure the respective stream compression registers.
Add support to calculate the register setting based on DSC params and
timing information and configure these registers.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Vi
Update headers from mesa commit:
commit 28ae397be111c37c6ced397e12d453a7695701bd
Author: Vinod Koul
Date: Fri Apr 1 16:53:04 2022 +0530
freedreno/registers: update dsi registers to support dsc
Display Stream compression (DSC) compresses the display stream in
host which
Add a mode valid callback for dsi_mgr for checking mode being valid in
case of DSC. For DSC the height and width needs to be multiple of slice,
so we check that here
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi.h |
This add the bits in RM to enable the DSC blocks
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 56 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
For DSC to work we typically need a 2,2,1 configuration. This should
suffice for resolutions up to 4k. For more resolutions like 8k this won't
work.
Also, it is better to use 2 LMs and DSC instances as half width results
in lesser power consumption as compared to single LM, DSC at full width.
The
Somehow documentation for num_dspp was missed, so add that
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/msm_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
inde
From: Dmitry Baryshkov
DPU supports different topologies for the case when multiple INTFs are
being driven by the single phys_enc. The driver defaults to using 3DMux
in such cases. Don't use it if DSC merge is used instead.
Suggested-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
Signed-off
We need to configure the encoder for DSC configuration and calculate DSC
parameters for the given timing so this patch adds that support by
adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++-
drivers/gpu/drm/msm/disp/dpu1/d
This adds SDM845 DSC blocks into hw_catalog
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog
In SDM845, DSC can be enabled by writing to pingpong block registers, so
add support for DSC in hw_pp
Reviewed-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 +++
.../gpu/drm/msm/disp/dpu1/dpu_hw_
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/Makefile | 1 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 13 ++
drivers/gpu/drm/
When DSC is enabled, we need to get the DSC parameters from the panel
driver, so add a dsc parameter in panel to fetch and pass DSC
configuration for DSI panels to DPU encoder, which will enable and
then configure DSC hardware blocks accordingly.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhin
Display Stream Compression (DSC) parameters need to be calculated. Add
helpers and struct msm_display_dsc_config in msm_drv for this
msm_display_dsc_config uses drm_dsc_config for DSC parameters.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu
Display Stream Compression (DSC) compresses the display stream in host which
is later decoded by panel. This series enables this for Qualcomm msm driver.
This was tested on Google Pixel3 phone which use LGE SW43408 panel.
The changes include DSC data and hardware block enabling for DPU1 then
supp
Hi Doug,
> On Wed, Mar 30, 2022 at 9:04 AM Sankeerth Billakanti
> wrote:
> >
> > Remove the unnecessary delay in executing the EV_HPD_INIT_SETUP
> event.
>
> Tell me more and put it in the commit message! Why did it used to be
> necessary and why is it no longer necessary? Inquiring minds want t
Hi Doug,
> On Wed, Mar 30, 2022 at 9:03 AM Sankeerth Billakanti
> wrote:
> >
> > @@ -1374,6 +1382,12 @@ static int dp_pm_resume(struct device *dev)
> > dp_catalog_ctrl_hpd_config(dp->catalog);
> >
> >
> > + if (dp->dp_display.connector_type ==
> DRM_MODE_CONNECTOR_DisplayPort)
> > +
Hi Doug,
> On Wed, Mar 30, 2022 at 9:03 AM Sankeerth Billakanti
> wrote:
> >
> > The source device should ensure the sink is ready before proceeding to
> > read the sink capability or performing any aux transactions. The sink
>
> s/performing/perform
>
> > will indicate its readiness by asserti
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