From: Rob Clark
Mesa attempts to allocate a cached-coherent buffer in order to determine
if cached-coherent is supported. Resulting in seeing this error message
once per process with newer mesa. But no reason for this to be more
than a debug msg.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/
From: Rob Clark
Reported-by: kernel test robot
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 8a2af3a27e33..dcde5eff931d
From: Rob Clark
When converting to use an idr to map userspace fence seqno values back
to a dma_fence, we lost the error return when userspace passes seqno
that is larger than the last submitted fence. Restore this check.
Reported-by: Akhil P Oommen
Fixes: a61acbbe9cf8 ("drm/msm: Track "seqno"
From: Rob Clark
We weren't dropping the submitqueue reference in all paths. In
particular, when the fence has already been signalled. Split out
a helper to simplify handling this in the various different return
paths.
Fixes: a61acbbe9cf8 ("drm/msm: Track "seqno" fences by idr")
Signed-off-by: R
From: Rob Clark
A couple of wait_fence related fixes.
Rob Clark (2):
drm/msm: Fix wait_fence submitqueue leak
drm/msm: Restore error return on invalid fence
drivers/gpu/drm/msm/msm_drv.c| 49 ++--
drivers/gpu/drm/msm/msm_gem_submit.c | 1 +
drivers/gpu/drm/
On Thu, Nov 11, 2021 at 4:13 AM Petri Latvala wrote:
>
> On Wed, Nov 10, 2021 at 11:00:41AM -0800, Rob Clark wrote:
> > On Wed, Nov 10, 2021 at 10:37 AM Rob Clark wrote:
> > >
> > > From: Rob Clark
> > >
> > > Add tests to exercise:
> > >
> > > 1. sw hangcheck timeout
> > > 2. gpu fault (hang) r
On Thu, Nov 11, 2021 at 7:54 AM Akhil P Oommen wrote:
>
> On 11/10/2021 10:25 PM, Rob Clark wrote:
> > On Wed, Nov 10, 2021 at 7:28 AM Akhil P Oommen
> > wrote:
> >>
> >> On 7/28/2021 6:36 AM, Rob Clark wrote:
> >>> From: Rob Clark
> >>>
> >>> Previously the (non-fd) fence returned from submit
On 11/9/2021 11:41 PM, Rob Clark wrote:
From: Rob Clark
Add a debugfs interface to ignore hw error irqs, in order to force
fallback to sw hangcheck mechanism. Because the hw error detection is
pretty good on newer gens, we need this for igt tests to test the sw
hang detection.
Signed-off-by:
On 11/9/2021 11:41 PM, Rob Clark wrote:
From: Rob Clark
Add some helpers for fence comparision, which handle rollover properly,
and stop open coding fence seqno comparisions.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_fence.h | 12
drivers/gpu/drm/msm/msm_gpu.c |
On 11/9/2021 11:41 PM, Rob Clark wrote:
From: Rob Clark
cur_ctx_seqno already does the same thing, but handles the edge cases
where a refcnt'd context can live after lastclose. So let's not have
two ways to do the same thing.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a2xx_gpu
On 11/10/2021 10:25 PM, Rob Clark wrote:
On Wed, Nov 10, 2021 at 7:28 AM Akhil P Oommen wrote:
On 7/28/2021 6:36 AM, Rob Clark wrote:
From: Rob Clark
Previously the (non-fd) fence returned from submit ioctl was a raw
seqno, which is scoped to the ring. But from UABI standpoint, the
ioctls
On Wed, Nov 10, 2021 at 10:42:11AM -0800, Rob Clark wrote:
> From: Rob Clark
>
> Signed-off-by: Rob Clark
Reviewed-by: Petri Latvala
> ---
> v2: Fix headerdoc comments
>
> lib/igt_debugfs.c | 17 +
> lib/igt_debugfs.h | 13 +
> 2 files changed, 30 insertions(+)
On Wed, Nov 10, 2021 at 11:00:41AM -0800, Rob Clark wrote:
> On Wed, Nov 10, 2021 at 10:37 AM Rob Clark wrote:
> >
> > From: Rob Clark
> >
> > Add tests to exercise:
> >
> > 1. sw hangcheck timeout
> > 2. gpu fault (hang) recovery
> > 3. iova fault recovery
> >
> > Signed-off-by: Rob Clark
> > -
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