mmu500 targets don't have a "cx_mem" region, set llc_mmio to NULL in that
case to avoid the IS_ERR() condition in a6xx_llc_activate().
Fixes: 3d247123b5a1 ("drm/msm/a6xx: Add support for using system cache on
MMU500 based targets")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6
Hi Rajeev,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on lee-backlight/for-backlight-next]
[also build test ERROR on drm-intel/for-linux-next drm-tip/drm-tip
drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next v5.12-rc8 next-20210423]
[cannot apply to drm/drm
Add backlight driver for the panels supporting backlight control
using DPCD registers on the DisplayPort aux channel.
Changes in v2:
- New (most of the code reused from drm_dp_aux_backlight.c of v1)
Signed-off-by: Rajeev Nandan
---
drivers/video/backlight/Kconfig| 7 +
drivers/vid
Add bindings for DisplayPort aux backlight driver.
Changes in v2:
- New
Signed-off-by: Rajeev Nandan
---
.../bindings/leds/backlight/dp-aux-backlight.yaml | 49 ++
1 file changed, 49 insertions(+)
create mode 100644
Documentation/devicetree/bindings/leds/backlight/dp-aux-
The backlight level of an eDP panel can be controlled through the AUX
channel using DPCD registers of the panel.
The capability for the Source device to adjust backlight characteristics
within the panel, using the Sink device DPCD registers is indicated by
the TCON_BACKLIGHT_ADJUSTMENT_CAPABLE bit
There shouldn't be any reason to ever use uncached over writecombine,
so just use writecombine for MSM_BO_UNCACHED.
Note: userspace never used MSM_BO_UNCACHED anyway
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_gem.c | 4 +---
include/uapi/drm/msm_drm.h| 2 +-
2 files changed,
Add a new cache mode for creating coherent host-cached BOs.
Signed-off-by: Jonathan Marek
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/ms
Use the same logic as the userspace mapping.
This fixes msm_rd with cached BOs.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_gem.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
msm_gem_get_vaddr() currently always maps as writecombine, so use the right
flag instead of relying on broken behavior (things don't actually work if
they are mapped as uncached).
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++--
drivers/gpu/drm/msm/adreno/a
No one knows what this is for anymore, so just remove it.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_gem.c | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index b199942266a2..09abda4
Add support for MSM_BO_CACHED_COHERENT, a coherent version of MSM_BO_CACHED
which is implemented by setting the IOMMU_CACHE flag.
Jonathan Marek (5):
drm/msm: remove unnecessary mmap logic for cached BOs
drm/msm: replace MSM_BO_UNCACHED with MSM_BO_WC for internal objects
drm/msm: use the ri
Increase the minor version to indicate that MSM_PARAM_SUSPENDS is supported.
Fixes: 3ab1c5cc3939 ("drm/msm: Add param for userspace to query suspend count")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
So that we can start using drm_dbg_*() for
drm_dp_link_train_channel_eq_delay() and
drm_dp_lttpr_link_train_channel_eq_delay().
Signed-off-by: Lyude Paul
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +-
drivers/gpu/drm/drm_dp_helper.c
So that we can start using drm_dbg_*() in
drm_dp_link_train_clock_recovery_delay().
Signed-off-by: Lyude Paul
Reviewed-by: Laurent Pinchart
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +-
drivers/gpu/drm/drm_dp_helper.c | 3 ++-
This is something that we've wanted for a while now: the ability to
actually look up the respective drm_device for a given drm_dp_aux struct.
This will also allow us to transition over to using the drm_dbg_*() helpers
for debug message printing, as we'll finally have a drm_device to reference
for d
Document qcom,dsi-phy-cphy-mode option, which can be used to control
whether DSI will operate in D-PHY (default) or C-PHY mode.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display/msm/dsi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bin
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 2 +
drivers/gpu/drm/msm/dsi/dsi_host.c| 34 -
drive
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
v2:
- rebased on DSI PHY reworks
- reworked getting cphy_mode in dsi_host.c
- documentation change in separate patch
Jonathan Marek (2):
drm/
Tested-by: Jonathan Marek
On 4/11/21 8:01 PM, Dmitry Baryshkov wrote:
msm_dsi_phy_get_clk_provider() always returns two provided clocks, so
return 0 instead of returning incorrect -EINVAL error code.
Fixes: 5d13459650b3 ("drm/msm/dsi: push provided clocks handling into a generic
code")
Signed
On Fri, Apr 23, 2021 at 4:58 AM Otavio Salvador
wrote:
>
> Hello all,
>
> We found this error when using Freedreno driver on an i.MX53 device
> with Wayland. Any idea how to fix this?
>
> [ 32.414110] [drm:msm_ioctl_gem_submit] *ERROR* invalid cmdstream size: 0
The invalid cmdstream size is som
Hello all,
We found this error when using Freedreno driver on an i.MX53 device
with Wayland. Any idea how to fix this?
[ 32.414110] [drm:msm_ioctl_gem_submit] *ERROR* invalid cmdstream size: 0
[ 39.177075]
[ 39.178617] ==
[ 39.184804] WA
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