On 2018-02-28 11:19, Sean Paul wrote:
These are already provided by drm atomic core.
In conjunction with the output fences removed earlier, this obsoletes
dpu_fence, and it can be entirely removed as well.
Change-Id: Ida4924a09c455d7a84bfee569bd0d2fb436418de
Signed-off-by: Sean Paul
Reviewed
On 2018-02-28 11:19, Sean Paul wrote:
Remove release/output/retire fences from the dpu driver. These are
already available via drm core's OUT_FENCE property.
Change-Id: Id4238d0b5457f2c8ee2e87bb7814e1850a573623
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c | 66 +-
On 2018-02-28 11:18, Sean Paul wrote:
This is another piece that can be moved out of atomic to facilitate
using
the atomic helpers.
Change-Id: I6dc3c4e5df508942bbc378c73a44e46e511b8469
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c |
On 2018-02-28 11:18, Sean Paul wrote:
Instead of duplicating whole swaths of atomic helper functions (which
are already out-of-date), just skip the encoder/crtc disables in the
.disable hooks.
Change-Id: I7bd9183ae60624204fb1de9550656b776efc7202
Signed-off-by: Sean Paul
Can you consider getti
Document the device tree bindings for the Adreno GMU device
available on Adreno a6xx targets.
Change-Id: I3cfd5fb35ab0045e39905ff12393006e60f1a124
Signed-off-by: Jordan Crouse
---
.../devicetree/bindings/display/msm/gmu.txt| 54 ++
.../devicetree/bindings/display/msm/
Add the nodes and other bits to describe the Adreno GPU and GMU
devices.
Change-Id: Ibf4dc0ebb0ac03d8b6b8e65747e142c440e70b0a
Signed-off-by: Jordan Crouse
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 120 +++
1 file changed, 120 insertions(+)
diff --git a/arch/arm6
Building on the sdm845 changes from Rajendra and SMMU changes from Vivek this
is an initial stab at the DT nodes for the sdm845 GPU and GMU (graphics
management unit) which is responsible for the direct power control of the GPU
including the companion arm-smmu-v2 compatible SMMU.
Please refer to h
Add a function to return the device node associated with a
specific opp which will facilitate detailing with custom
properties in client drivers.
Signed-off-by: Jordan Crouse
---
drivers/opp/of.c | 20
include/linux/pm_opp.h | 6 ++
2 files changed, 26 insertions(
From: Sharat Masetty
Add initial register headers for A6XX targets.
Change-Id: If7b37634aed55c8e05ac26465d628205b6130f09
Signed-off-by: Sharat Masetty
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 1600 +
drivers/gpu/drm/msm/adreno/a6
a6xx GPU support for drm/msm - follow along here:
https://patchwork.freedesktop.org/series/37428/
Per suggestions from various folks for the associated device tree changes for
the sdm845 GPU (coming immediately after this) add a new opp function to query
the device tree node for a specific opp so
Add support for the A6XX family of Adreno GPUs. The biggest addition
is the GMU (Graphics Management Unit) which takes over most of the
power management of the GPU itself but in a ironic twist of fate
needs a goodly amount of management itself. Add support for the
A6XX core code, the GMU and the H
On 2018-02-23 13:34, abhin...@codeaurora.org wrote:
Alright, found it
https://cgit.freedesktop.org/~seanpaul/dpu-staging/commit/?h=mtp-testing&id=34906195473f9e04601c49a45e3fedce0132eb7e
Thanks
Abhinav
Reviewed-by: Abhinav Kumar
On 2018-02-23 07:06, Sean Paul wrote:
On Thu, Feb 22, 2018 at
On 2018-03-02 12:17, abhin...@codeaurora.org wrote:
On 2018-03-02 12:06, jsa...@codeaurora.org wrote:
On 2018-02-26 08:49, Sean Paul wrote:
They're not used, so let's get rid of them.
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
Reviewed-by: Abhinav Kumar
---
include/drm/d
On 2018-03-02 12:06, jsa...@codeaurora.org wrote:
On 2018-02-26 08:49, Sean Paul wrote:
They're not used, so let's get rid of them.
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
include/drm/drm_connector.h | 19 ---
1 file changed, 19 deletions(-)
diff --gi
On 2018-02-26 08:49, Sean Paul wrote:
They're not used, so let's get rid of them.
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
include/drm/drm_connector.h | 19 ---
1 file changed, 19 deletions(-)
diff --git a/include/drm/drm_connector.h b/include/drm/drm_c
On 2018-02-21 13:42, Sean Paul wrote:
We need to have a discussion about how to introduce this in a way that
it can be leveraged by other platforms/userspaces. For now, remove
support since we don't need it yet.
Signed-off-by: Sean Paul
Reviewed-by: Jeykumar Sankaran
---
drivers/gpu/drm/d
On Fri, Mar 02, 2018 at 05:57:21PM +, Robin Murphy wrote:
> On 21/02/18 22:59, Jordan Crouse wrote:
> >Allow a SMMU device to opt into allocating a TTBR1 pagetable.
> >
> >The size of the TTBR1 region will be the same as
> >the TTBR0 size with the sign extension bit set on the highest
> >bit in
On 21/02/18 22:59, Jordan Crouse wrote:
Allow a SMMU device to opt into allocating a TTBR1 pagetable.
The size of the TTBR1 region will be the same as
the TTBR0 size with the sign extension bit set on the highest
bit in the region unless the upstream size is 49 bits and then
the sign-extension b
On Thu, Mar 01, 2018 at 04:52:35PM -0800, Jeykumar Sankaran wrote:
> Implementation of partial update in DPU DRM is heavily
> dependent on custom properties and dsi hooks. Removing the
> support for now. We may need to revisit the support in the
> future.
>
> changes since v1:
> - get away w
On Fri, Mar 02, 2018 at 12:27:58PM +, Jean-Philippe Brucker wrote:
> On 21/02/18 22:59, Jordan Crouse wrote:
> [...]
> > +int iommu_sva_alloc_pasid(struct iommu_domain *domain, struct device *dev)
> > +{
> > + int ret, pasid;
> > + struct io_pasid *io_pasid;
> > +
> > + if (!domain->ops->
On Fri, Mar 02, 2018 at 12:25:48PM +, Jean-Philippe Brucker wrote:
> Hi Jordan,
>
> Thank you for this, SMMUv3 and virtio-iommu need these SVA patches as well.
>
> On 21/02/18 22:59, Jordan Crouse wrote:
> [...]> diff --git a/include/linux/iommu.h b/include/linux/iommu.h
> > index e2c49e583d8
On Thu, Mar 01, 2018 at 07:37:10PM -0500, Rob Clark wrote:
> On Thu, Mar 1, 2018 at 3:37 PM, wrote:
> > On 2018-03-01 07:27, Sean Paul wrote:
> >>
> >> On Wed, Feb 28, 2018 at 08:07:00PM -0800, jsa...@codeaurora.org wrote:
> >>>
> >>> On 2018-02-28 11:19, Sean Paul wrote:
> >>> > Moving further t
On 21/02/18 22:59, Jordan Crouse wrote:
Add a new domain attribute to enable the TTBR1 pagetable for drivers
and devices that support it. This will enabled using a TTBR1 (otherwise
known as a "global" or "system" pagetable for devices that support a split
pagetable scheme for switching pagetable
On 21/02/18 22:59, Jordan Crouse wrote:
[...]> +static int install_pasid_cb(int pasid, u64 ttbr, u32 asid, void *data)
> +{
> + struct pasid_entry *entry = kzalloc(sizeof(*entry), GFP_KERNEL);
> +
> + if (!entry)
> + return -ENOMEM;
> +
> + entry->pasid = pasid;
> + entr
On 21/02/18 22:59, Jordan Crouse wrote:
[...]
> +int iommu_sva_alloc_pasid(struct iommu_domain *domain, struct device *dev)
> +{
> + int ret, pasid;
> + struct io_pasid *io_pasid;
> +
> + if (!domain->ops->pasid_alloc || !domain->ops->pasid_free)
> + return -ENODEV;
> +
> +
Hi Jordan,
Thank you for this, SMMUv3 and virtio-iommu need these SVA patches as well.
On 21/02/18 22:59, Jordan Crouse wrote:
[...]> diff --git a/include/linux/iommu.h b/include/linux/iommu.h
> index e2c49e583d8d..e998389cf195 100644
> --- a/include/linux/iommu.h
> +++ b/include/linux/iommu.h
>
Add CP_SECURE_MODE and CP_SET_PSEUDO_REG opcodes needed for A6xx
hardware features.
Signed-off-by: Sharat Masetty
---
rnndb/adreno/adreno_pm4.xml | 5 +
1 file changed, 5 insertions(+)
diff --git a/rnndb/adreno/adreno_pm4.xml b/rnndb/adreno/adreno_pm4.xml
index 3621f07..c1a82da 100644
--- a
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