Hi list,
I have multiple FreeBSD firewalls with carp working well. I have no problem
and the vast majority of firewalls works perfectly.
But now, I'm with problems with a simple firewall cluster with carp that
the state randomly goes to MASTER and randomly returns to BACKUP.
Looking to the L1/L2
2013/3/18 Damien Fleuriot
>
> On 18 Mar 2013, at 22:22, Rafael Ganascim wrote:
>
> > Hi list,
> >
> > I have multiple FreeBSD firewalls with carp working well. I have no
> problem
> > and the vast majority of firewalls works perfectly.
> >
> > B
Hi list,
I was looking in the igb driver that I use on some Intel nics
(dualport and quadport gigabit) and in the source code, the feature:
/*
** Header split causes the packet header to
** be dma'd to a seperate mbuf from the payload.
** this can have memory alignment benefits. But
** another pl
> Jack
>
>
> On Wed, Feb 29, 2012 at 5:10 AM, Rafael Ganascim
> wrote:
>>
>> Hi list,
>>
>> I was looking in the igb driver that I use on some Intel nics
>> (dualport and quadport gigabit) and in the source code, the feature:
>>
>>
Hi list,
I'm planning and testing a new FreeBSD router, with vlans and carp
interfaces. There are a lot of vlans, with high vlan IDs. We have, for
example:
dot1q vlan id: 1530
Iface igb0
vlan1530
carp1530
vhid 10
What do you think in change the carp code to support vhid above 255 (just to
EGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> Rafael Ganascim wrote:
> > Hi list,
> >
> > I'm planning and testing a new FreeBSD router, with vlans and carp
> > interfaces. There are a lot of vlans, with high vlan IDs. We have, for
> > example:
> >
Hi,
I think that this is an old question
I think that Intel 82575 (and another models) hardware are capable of
multiple queues both on the receive and the send side. Is it right?
Currently the processing of packets is limited to one CPU per NIC.
Can we have multiple taskq processes for one N
Hi list,
I have a doubt (don't encountered on google) about what is better for a
FreeBSD Router: use a 32bits SMP kernel or an amd64? I know that exists some
differences, but generaly, what is better and why?
I have a hardware with Xeon Dual processor.
Thanks,
Rafael
__
Hi list,
Can the bge driver use more than one MSI message? If possible, what the
advantage of this on a SMP system (better CPU distribution on interrupts?)?
I have an Broadcom BCM5703X, with 8 MSI messages:
--
b...@pci0:1:2:0:class=0x02 card=0x00cb0e11 chip=0x16a714e4 rev=0x02
hdr=0x00