Thanks Michael.
Having looked at that document, the bit masks there are incorrect.
In RFC3168, the CWR bit is supposed to be sent once only (and ideally as
early as possible). The documented bitmasks for the First, Mid and Last
segments don't make sense in that case:
0xFF6 0xFF6 0xF7F
Thes
> On Dec 20, 2023, at 12:15, Scheffenegger, Richard wrote:
>
> Hi,
>
> I am curious if anyone here has expirience with the handling of ECN in
> TSO-enabled drivers/hardware...
Some data pointer if I read the specification correctly.
Have a look at the specification of the 10GBit/sec card ix:
ht
