Hi everyone,
Don't know where I should ask this, so I'll just try with this mailing
list as a first attempt. I have implemented an IFLIB based network
device driver for a Xilinx FPGA card with a custom firmware,
everything seems to work fine except for the number of RX/TX queues
selected by IFLIB
Hi everyone,
Reading the IFLIB's code I noticed this "ifmp_ring" data structure,
but by checking the "mp_ring.c/h" files, I cannot see a single comment
nor any documentation whatsoever about what that really is (I guess
some kind of lock-free ring buffer? but then why not using
"buf_ring"?), and/
I have a NIC (a SmartNIC actually) for which I have to implement a
driver, which in addition to RX and TX rings exposes also completion
CMPT rings. Due to this additional complication (the CMPT rings), I'm
not sure how appropriate it is to implement such a driver via the
IFLIB framework. Does anyon
