On Tuesday 20 May 2008 02:58:49 pm Andriy Gapon wrote:
> on 20/05/2008 18:24 John Baldwin said the following:
> > On Tuesday 20 May 2008 09:37:54 am Andriy Gapon wrote:
> >> BTW, I understand that there is a difference between hard and soft reset
> >> in terms of hardware signals being asserted, bu
on 20/05/2008 18:24 John Baldwin said the following:
On Tuesday 20 May 2008 09:37:54 am Andriy Gapon wrote:
BTW, I understand that there is a difference between hard and soft reset
in terms of hardware signals being asserted, but I don't quite
understand general consequences. I.e. what is a prac
On Tuesday 20 May 2008 09:37:54 am Andriy Gapon wrote:
> on 20/05/2008 00:51 John Baldwin said the following:
> > So, the comment is correct and not the code. Curiously enough,
OpenSolaris
> > does the same thing (it writes 0x2 followed by 0x6), but it has some sort
of
> > comment which implies
on 20/05/2008 00:51 John Baldwin said the following:
> So, the comment is correct and not the code. Curiously enough, OpenSolaris
> does the same thing (it writes 0x2 followed by 0x6), but it has some sort of
> comment which implies that you have to do a write to set or clear bit 1
> before sett
On Monday 19 May 2008 10:32:02 am John Baldwin wrote:
> On Monday 12 May 2008 01:23:28 pm RW wrote:
> > On Mon, 12 May 2008 17:34:35 +0300
> >
> > Andriy Gapon <[EMAIL PROTECTED]> wrote:
> > > This is not a real issue, just a code clarification.
> > >
> > > First a snippet from sys/i386/i386/vm_mac
On Monday 12 May 2008 01:23:28 pm RW wrote:
> On Mon, 12 May 2008 17:34:35 +0300
>
> Andriy Gapon <[EMAIL PROTECTED]> wrote:
> > This is not a real issue, just a code clarification.
> >
> > First a snippet from sys/i386/i386/vm_machdep.c, cpu_reset_real()
> > /*
> > * Attempt to force a reset via
On Mon, 12 May 2008 17:34:35 +0300
Andriy Gapon <[EMAIL PROTECTED]> wrote:
>
> This is not a real issue, just a code clarification.
>
> First a snippet from sys/i386/i386/vm_machdep.c, cpu_reset_real()
> /*
> * Attempt to force a reset via the Reset Control register at
> * I/O port 0xcf9. Bit
This is not a real issue, just a code clarification.
First a snippet from sys/i386/i386/vm_machdep.c, cpu_reset_real()
/*
* Attempt to force a reset via the Reset Control register at
* I/O port 0xcf9. Bit 2 forces a system reset when it is
* written as 1. Bit 1 selects the type of reset to a
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