Re: BUS DMA sync

2003-09-25 Thread M. Warner Losh
In message: <[EMAIL PROTECTED]> Vincent Jardin <[EMAIL PROTECTED]> writes: : What's about PREREAD ? What kind of CPU synchronization is required prior a : DMA read ? There is no cache during a device to host memory process, isn't it : ? There is on MIPS. Warner _

Re: BUS DMA sync

2003-09-24 Thread Vincent Jardin
Thanks, What's about PREREAD ? What kind of CPU synchronization is required prior a DMA read ? There is no cache during a device to host memory process, isn't it ? Vincent Le Mercredi 24 Septembre 2003 23:54, Maxime Henrion a écrit : > Vincent Jardin wrote: > > Hi, > > > > I try to understan

Re: BUS DMA sync

2003-09-24 Thread Maxime Henrion
Vincent Jardin wrote: > Hi, > > I try to understand the purpose of the PRE sync (BUS_DMASYNC_PREREAD, > BUS_DMASYNC_PREWRITE). > > I understand POST synchronization (BUS_DMASYNC_POSTREAD, > BUS_DMASYNC_POSTWRITE) when a device to memory or a memory to device > transfert needs to be synchroniz

BUS DMA sync

2003-09-24 Thread Vincent Jardin
Hi, I try to understand the purpose of the PRE sync (BUS_DMASYNC_PREREAD, BUS_DMASYNC_PREWRITE). I understand POST synchronization (BUS_DMASYNC_POSTREAD, BUS_DMASYNC_POSTWRITE) when a device to memory or a memory to device transfert needs to be synchronized. However, what does a synchronizati