Hi and thanks for the answers,
This feature seems to be a compiler intrinsic at least in the Intel C
> compiler. We don't have anything similar, so you have to fall back either
> to an asm procedure or a line of inline assembler. The compiler is also
> not doing an optimization similar to this. Fr
Hi,
On Fri, 3 Nov 2017, Matias Vara wrote:
> Hello, I think it would be better if I put my question in context. In
> order to tell the processor that we are in a loop, the pause instruction
> could be used (also I think the "rep nop" produces the same opcode).
> This tells the processor that we
I want to implement the cpu_relax() function in order to use it
inside loops. However before, I would like to know if the fpc
compiler is doing an optimization of this kind.
I don't think one would you use that "inside a loop" or "to improve branching" but rather inside a
wait-loo
Hello,
I think it would be better if I put my question in context. In order to
tell the processor that we are in a loop, the pause instruction could be
used (also I think the "rep nop" produces the same opcode). This tells the
processor that we are in a loop so it improves the access to the cache
Hello everyone,
I want to implement the cpu_relax() function in order to use it inside
loops. However before, I would like to know if the fpc compiler is doing an
optimization of this kind.
Kinds regards, Matias.
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