requests like this, even though i find your
explanation as to why you think VxWorks users (what vxworks users would
even know of flashrom?) will not use flashrom rather hairy. It's not
nearly so easy to actually make such a change, as such a license change
entails getting permission from
lways have to do some of that.
That's 1520 commits where you have to go and figure out the real author,
and only a third or so is using signed-off-by statements.
Good luck.
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashrom.org
http://www.flashrom.org/mailman/listinfo/flashrom
uot;VIA Southbridge
marketing name with VT removed".
This DMI string is not unique at all.
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashrom.org
http://www.flashrom.org/mailman/listinfo/flashrom
On Sat, Apr 28, 2012 at 02:06:48AM +0200, Stefan Tauner wrote:
> On Sat, 28 Apr 2012 01:42:37 +0200
> Luc Verhaegen wrote:
>
> > On Sat, Apr 28, 2012 at 01:30:53AM +0200, Stefan Tauner wrote:
> > > The PCI IDs are generic VIA IDs. Only Biostar IDs are those of the LO
On Sat, Apr 28, 2012 at 12:50:19PM +0200, Stefan Tauner wrote:
> On Sat, 28 Apr 2012 02:25:02 +0200
> Luc Verhaegen wrote:
>
> > Surely a specific board name can still be provided on the command line
> > for horribly broken bioses like this?
>
> yes, thanks for t
;
> Where SPI is the internal SPI chip on your motherboard.
> If (using flashrom as the backend) the linux kernel supports your flash
> chip, you could just use dd.
>
> What does the community think of this idea?
Where would you stick the:
On Thu, Jan 30, 2014 at 02:56:59PM +, David Woodhouse wrote:
> On Thu, 2014-01-30 at 15:22 +0100, Luc Verhaegen wrote:
> >
> > Where would you stick the:
> > * chipset enables
> > * board enables
>
> In drivers/mtd/maps/ alongside the existing ones?
I can
; Elmar
>
> P.S.: if my hint should not have been particularely helpful I would like to
> know about that as well ...
I recently had a quick look at something related, and noticed that there
is a well-defined ATAPI call to flash the firmware. It can be found in
the pub
; Elmar
>
> P.S.: if my hint should not have been particularely helpful I would like to
> know about that as well ...
/sbin/msecli is where the magic is, and strings shows that that is
filled with a load of atapi/smart stuff.
Luc Verhaegen.
__
tomatically) should note the BBB and directly link to its page.
> Will be like that... sometimes in the future.
Add a programmer category, and have the categories listed on the
supported hardware page.
Also, Sam, it's a wiki.
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashrom.org
https://www.flashrom.org/mailman/listinfo/flashrom
On Sat, Mar 18, 2017 at 05:52:28PM +, Sam Kuper wrote:
> On 18/03/2017, Luc Verhaegen wrote:
> > On Sat, Mar 18, 2017 at 05:52:15PM +0100, Stefan Tauner wrote:
> >> On Sat, 18 Mar 2017 16:45:14 +
> >> Sam Kuper wrote:
> >> The existence of that p
ktop.org/~libv/flash_enable_bios_reverse_engineering_(FOSDEM2010_-_slides).pdf
Your BIOS is an award and should be trivial.
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashrom.org
https://mail.coreboot.org/mailman/listinfo/flashrom
On Sun, Feb 25, 2018 at 11:49:40AM +0100, Luc Verhaegen wrote:
> On Thu, Feb 22, 2018 at 08:40:58PM +0100, Björn Tantau wrote:
> >
> > Reverse engineering seems to be the only option left. Unfortunately
> > I'm not well versed in these arcane arts. ;-)
>
> You
On Mon, Mar 19, 2018 at 05:01:06PM +0100, Björn Tantau wrote:
> Am 19.03.2018 um 00:08 schrieb Luc Verhaegen:
> >
> >My current hypothesis: smsc at 0x480
> >
> >Action required: 0x48E |= 0x10.
> Do you want to scan for Super I/O sensors? (YES/no): Probing for Supe
On Tue, Mar 20, 2018 at 12:22:02PM +0100, Björn Tantau wrote:
>
>
> Am 19. März 2018 18:21:36 MEZ schrieb Luc Verhaegen :
> >On Mon, Mar 19, 2018 at 05:01:06PM +0100, Björn Tantau wrote:
> >> Am 19.03.2018 um 00:08 schrieb Luc Verhaegen:
> >> >
> &
On Tue, Mar 20, 2018 at 02:27:54PM +0100, Luc Verhaegen wrote:
>
> What this board needs is a call to intel_ich_gpio20_raise();
>
> Will provide a patch later today.
Attached.
> I am a bit worried though that the lpc io BAR is empty in your lspci. I
> am not sure whether
On Wed, Mar 28, 2018 at 04:24:25PM +0200, Idwer Vollering wrote:
> I took the liberty to submit this change to gerrit;
> https://review.coreboot.org/#/c/flashrom/+/25396/
Please fix the author.
Luc Verhaegen.
___
flashrom mailing list
fl
On Wed, Mar 28, 2018 at 06:49:09PM +0200, Luc Verhaegen wrote:
> On Wed, Mar 28, 2018 at 04:24:25PM +0200, Idwer Vollering wrote:
> > I took the liberty to submit this change to gerrit;
> > https://review.coreboot.org/#/c/flashrom/+/25396/
>
> Please fix the author.
T
s and will come back with
further questions or make small fixes as needed. Feel free to poke me
with any questions or anything, both on irc (libv@freenode) and on
email (hardware-devroom-mana...@fosdem.org).
That's about it. Hope to see you all at FOSDEM :)
Luc
uture viability of the project.
Sounds like you are making an fwupd problem into a flashrom problem.
Luc Verhaegen.
___
flashrom mailing list -- flashrom@flashrom.org
To unsubscribe send an email to flashrom-le...@flashrom.org
On Wed, Oct 28, 2020 at 03:10:47PM +0100, Luc Verhaegen wrote:
> On Wed, Oct 28, 2020 at 01:41:30PM +, Richard Hughes wrote:
> > On Wed, 28 Oct 2020 at 12:20, Nico Huber wrote:
> > > So we didn't need these things before. Why do we need them now?
> >
> &g
efile, and removing the
> subproject would force us to remove flashrom support from almost all
> the CI systems we test fwupd with.
Is meson unable to call `make` in a subdirectory?
Luc Verhaegen.
___
flashrom mailing list -- flashrom@flashrom.org
To unsubscribe send an email to flashrom-le...@flashrom.org
d path on top of that a few years later. They never had
anything reliable before the hardware was totally obsolete.
Also, what does one gain from two versions? Are there not effectively
two version of flashrom already? The google one, and the formal one? Is
this not just a veiled attempt to chris
der chipsets
or board enables.
To me, this reeks of an unwillingness to deal with supporting slightly
older hw, or to deal with chipsets/superios/boards at a time where we
backslid into depending on BIOS hooks again.
Luc Verhaegen.
___
flashrom mailing list
ained and containing useful information, for projects 100x as
big?
With the limited amount of manpower that is available for flashrom,
don't we have better things to do?
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashrom.org
http://www.flashrom.org/mailman/listinfo/flashrom
ion, if there are
> multiple revisions), and a link to the official BIOS download.
>
> Thanks!
>
> Josh
That would astound me, as i have owned this hardware since 2005, 2 years
before i created board_enable.c.
This is the email from that time where i also confirm the fx43g as
wo
nd we would like to make sure
> that
> * matches are unique.
> *
> * If PCI IDs are not sufficient for board matching, the match can be further
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashrom.org
http://www.flashrom.org/mailman/listinfo/flashrom
t; * Shuttle AK31
These two need testing, but the AK31 seems pretty safe and will be
committed tomorrow together with an addition to the board_notes table
about this board still needing testing.
The intel_piix4 thing does need a test though, it is rather subs
On Mon, Jul 06, 2009 at 07:26:40PM +0200, Luc Verhaegen wrote:
> Resending this patch to the newly formed flashrom ml. Ron already
> kindly acked this patch.
>
> Mateusz, the owner of this board gave me a brief comment on irc stating
> that it didn't work. Which is also t
Board enable for Shuttle FN25 (SN25P).
Shuttle SFF PC is SN25P, board FN25, AMD socket 939 with an nForce4
chipset.
Config register 0x92 on the ISA bridge needs to be cleared for TBL#
to be raised. No information about individual bits of this register
is currently available.
Signed-off-by: Luc
/
> @@ -2148,10 +2151,23 @@
> .model_id = SST_49LF004A,
> .total_size = 512,
> .page_size = 64 * 1024,
> - .tested = TEST_OK_PREW,
> + .tested = TEST_OK_PRW,
Can we not consider E as tested here? I believe yo
On Wed, Sep 23, 2009 at 02:11:27PM +0200, Carl-Daniel Hailfinger wrote:
> On 23.09.2009 13:44, Luc Verhaegen wrote:
> >
> > Can we not consider E as tested here? I believe you got ulf to test
> > both, and with the board enable, even the 64k block erase succeeded.
> >
t; > Flash Chip: SST39SF020A (PLCC)
> > Chipset: Via VT8235
> >
>
>
> Enjoy!,
>
>
> Udu E. Ogah
This is an AMI, so I will need a dump of the F segment.
Please run:
dd if=/dev/mem of=/tmp/asrock_k7vt4a_f_segment.rom bs=64k count=1 skip=15
Thanks
Luc Verhaegen.
ng 'Unknown flash type'), but flashrom did. ;)
>
> HTH,
> Jelle Geerts
This board touches the superio. Please run superiotool so we know what
chip this is, and so that the rest of the code can be developed to
enable access to your flash.
Luc Verhaegen.
_
Bios Version: P1.90
> Cheers,
>
> --
> Udu Ogah
Another AMI, so i will once again need the F segment dumped.
Please run:
dd if=/dev/mem of=/tmp/asrock_k7s41gx_f_segment.rom bs=64k count=1 skip=15
Thanks,
Luc Verhaegen.
___
flashr
0:14.3, 0x48) |= 0x21; /* ISA Bridge */
io(0xC6F) |= 0x40;
io(0xCD6) = 0x03;
io(0xCD7) &= ~0x01;
Unzipped lspci attached for search engine indexing.
Luc Verhaegen.
00:00.0 Host bridge [0600]: Advanced Micro Devices [AMD] RS780 Host Bridge
[1022:9600]
Subsystem: Advanced Micro Devi
d Controller [1095:6112]
> 01:0d.0 FireWire (IEEE 1394) [0c00]: Agere Systems FW323 [11c1:5811] (rev 61)
> (prog-if 10 [OHCI])
> Subsystem: EPoX Computer Co., Ltd. Unknown device [1695:9015]
Match #2
Please test the attached patch.
When succesfull, please reply with
Acked-by: ##
On Mon, Oct 05, 2009 at 03:25:12AM +0200, Luc Verhaegen wrote:
>
> Please test the attached patch.
>
> When succesfull, please reply with
> Acked-by: ##InsertRealNameHere##
>
> Luc Verhaegen.
Patch is slightly off.
Fixed up version attached.
Luc Verhaegen.
Board ena
On Mon, Oct 05, 2009 at 03:40:16AM +0200, Luc Verhaegen wrote:
>
> Patch is slightly off.
>
> Fixed up version attached.
>
> Luc Verhaegen.
Since we will soon have 3 very similar board enables for nvidia MCPs
i have altered the patch.
Luc Verhaegen.
Board enable for EPoX E
can easily trump that as i believe he was working
for SuSE (already/still) at the time.
Also, please use your real and full name for acknowledging patches later
on.
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashrom.org
http://www.flashrom.org
.
You might want to work with them to get your pciids in their list (my
guess is that they need you to dig through some windows driver .inf
files.)
Thanks,
Luc Verhaegen.
Chipset support for the nVidia nForce 4.
Add pciids for the new isa bridge, and hook it to the nforce2
chipset enable.
Signed
On Tue, Sep 29, 2009 at 05:31:57PM -0400, Allan Bjorklund wrote:
> Hello,
>
> I saved a copy of my existing BIOS image with: flashrom -r original_bios.bin
Can you send me (directly) a copy of this image?
Luc Verhaegen.
___
flashrom mai
On Mon, Oct 05, 2009 at 02:30:29PM +0200, Carl-Daniel Hailfinger wrote:
> On 25.09.2009 00:18, Carl-Daniel Hailfinger wrote:
> > On 07.07.2009 17:12, Robert Millan wrote:
> >
> >> On Tue, Jul 07, 2009 at 03:10:32PM +0200, Luc Verhaegen wrote:
> >>
> >
On Mon, Oct 05, 2009 at 03:24:47PM +0200, Martin S. wrote:
> On Mon, 2009-10-05 at 13:52 +0200, Luc Verhaegen wrote:
> > Can you attach the output of lspci -vvnnxxx?
> >
>
> Attached.
>
> > I will soon send in a patch for the chipset enable.
> >
>
>
On Mon, Oct 05, 2009 at 05:16:43PM +0200, Martin S. wrote:
> Acked-by: Martin Szulecki
-> r744.
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashrom.org
http://www.flashrom.org/mailman/listinfo/flashrom
On Mon, Oct 05, 2009 at 05:45:35PM +0200, Martin S. wrote:
> Acked-by: Martin Szulecki
>
-> r745
Thanks a bunch!
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashrom.org
http://www.flashrom.org/mailman/listinfo/flashrom
On Mon, Oct 05, 2009 at 01:45:09PM +0200, Luc Verhaegen wrote:
>
> Since we will soon have 3 very similar board enables for nvidia MCPs
> i have altered the patch.
>
> Luc Verhaegen.
Another re-spin, as part of this code got committed with r745.
Luc Verhaegen.
Board enable fo
On Mon, Oct 05, 2009 at 06:34:28PM +, . . wrote:
>
> Acked-by: Eddie Vanhove
>
> Works great, new bios is in place.
> Excellent program is all I can say, really deserves more public attention.
Thanks, r746.
Luc Verhaegen.
___
f
your bios chip really
has one of its write protection lines set.
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashrom.org
http://www.flashrom.org/mailman/listinfo/flashrom
gt; Bios Version: P1.90
>
> r...@ubuntu:~# lspci
> 00:00.0 Host bridge: Silicon Integrated Systems [SiS] 741/741GX/M741 Host
> (rev 03)
> WARNING: No chipset found. Flash detection will most likely fail.
Aha. This is an SiS 741 without even chipset support. Let's dig that one
out
On Tue, Oct 06, 2009 at 12:49:13PM +0200, Luc Verhaegen wrote:
> On Thu, Sep 03, 2009 at 12:29:46AM +0100, Putlinuxonit wrote:
> > Hi,
> >
> > Just want to report a non-working board - the Asrock K7S41GX, tested with
> > flashrom r711 and superiotool r4623.
> &
Neo3)
VIA EPIA-N/NL
VIA PC3500G
The following two devices are known to be valid, as they predate pci
subsystem ids: the ASUS P5A (which i own) and the EPoX EP-BX3.
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashrom.org
http://www.flashrom.
On Tue, Oct 06, 2009 at 04:27:52PM +0200, Carl-Daniel Hailfinger wrote:
> On 07.07.2009 15:10, Luc Verhaegen wrote:
> > + /* dual function that need special enable. */
> > + if ((gpo >= 22) && (gpo <= 26)) {
> > + tmp = pci_read_long(dev, 0xB0);
Allan, please try this patch.
If this works, please reply with:
Acked-by: Allan Bjorklund
Thanks,
Luc Verhaegen.
Board enable for Asus P4B266LM.
Found in the Sony Vaio PCV-RX650.
Uses the same board enable (but different ICH) as the Asus P4P800-E.
Signed-off-by: Luc Verhaegen
Index
ou send in lspci -vvnnxxx on both boards?
Thanks,
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashrom.org
http://www.flashrom.org/mailman/listinfo/flashrom
least have the checksum be
correct and hopefully have the machine boot again.
But the final solution for Yuri is probably getting a new chip from
somewhere.
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashrom.org
http://www.flashrom.org/mailman/listinfo/flashrom
s again! Ulf
>
> On Wed, 2009-09-23 at 10:26 -0300, Luc Verhaegen wrote:
> > On Wed, Sep 23, 2009 at 10:14:47AM -0300, Ulf Mehlig wrote:
> > > Thanks for the patch, and many thanks again for helping me out
> > > yesterday!
> > >
> > > All the best, U
A first: removal of what might be a working board enable still.
Long story short; it's horrible and i do not want to spend any time on
cleaning it up. We have better things to do.
Luc Verhaegen.
Remove board enable for the Asus P5A.
Asus P5A was a very popular supersocket7 board more t
On Wed, Oct 21, 2009 at 05:43:50PM +0200, Luc Verhaegen wrote:
> A first: removal of what might be a working board enable still.
>
> Long story short; it's horrible and i do not want to spend any time on
> cleaning it up. We have better things to do.
>
> Luc Verhaegen.
On Tue, Oct 06, 2009 at 01:30:56PM +0200, Luc Verhaegen wrote:
>
> Give this one a whirl.
>
> Luc Verhaegen.
> Add chipset support for SiS963.
>
> Just touches two bits, but no docs as per SiS usual.
>
> Signed-off-by: Luc Verhaegen
Board: Make Acorp 6A815EPD autodetectable.
Add subsystem id for hostbridge match for Acorp 6A815EPD; even though
it reads "intel", NULL, this, together with the promise ultra100 chip
and subsystem ids, should form a unique enough match for us to depend
upon.
Signed-off-by: Luc Verhae
board since I upgraded the
> machine to a NForce4 set. If I find it, i'll try to send you the dumps
> you need.
>
> On Sat, Oct 17, 2009 at 2:58 PM, Luc Verhaegen wrote:
> > Hi Sean,
> >
> > I have some questions about your kt4v/kt4ultra board enable:
> >
a run too?
I would like to see at least 4 of these boards get an Ack before this
can be committed.
Thanks all, now i can send in at least two more board enables which go
on top of this stuff.
Luc Verhaegen.
Boards: Unify all intel ICH GPIO setting in one function.
Instead of scheme-like
gt; + (curopcodes->opcode[oppos].atomic - 1 == preoppos))
> continue;
> - }
> }
>
> ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt,
>
>
> --
> Developer quote of the week:
> "We are juggling to
On Thu, Oct 22, 2009 at 03:50:53AM +0200, Carl-Daniel Hailfinger wrote:
> On 22.10.2009 02:56, Luc Verhaegen wrote:
> > Ok, big change here which will require several of the people on the list
> > below to test and Ack this patch. But one has to admit; the result i
On Fri, Oct 23, 2009 at 02:42:16AM +0200, Carl-Daniel Hailfinger wrote:
> On 23.10.2009 01:41, Carl-Daniel Hailfinger wrote:
> > On 22.10.2009 15:16, Luc Verhaegen wrote:
> >
> >> Also, we are no longer fully on par with the previous board enables
> >> which us
On Thu, Oct 22, 2009 at 11:44:24PM +0200, Uwe Hermann wrote:
> On Thu, Oct 22, 2009 at 03:16:16PM +0200, Luc Verhaegen wrote:
> > > > Ok, big change here which will require several of the people on the
> > > > list
> > > > below to test and Ack this pat
On Fri, Oct 23, 2009 at 01:46:52AM +0200, Carl-Daniel Hailfinger wrote:
> On 22.10.2009 23:44, Uwe Hermann wrote:
> > On Thu, Oct 22, 2009 at 03:16:16PM +0200, Luc Verhaegen wrote:
> >
> > I agree we should drop the totally useless 0x48 register index, 0x0c
> > offset,
On Fri, Oct 23, 2009 at 01:41:41AM +0200, Carl-Daniel Hailfinger wrote:
> On 22.10.2009 15:16, Luc Verhaegen wrote:
> > We are writing flashrom here. We are dealing with bits and pci-ids. Lots
> > of them. If we cannot see the important things because we abstracted too
> &
On Fri, Oct 23, 2009 at 06:49:18PM +0200, Carl-Daniel Hailfinger wrote:
> On 23.10.2009 16:27, Luc Verhaegen wrote:
> > On Fri, Oct 23, 2009 at 01:41:41AM +0200, Carl-Daniel Hailfinger wrote:
> >
> > Boards are very heavily tied to chipsets. Quite often, southbridge
>
based on
more general infrastructure. Can you give this patch a whirl too?
You will have to apply this patch here first though:
http://patchwork.coreboot.org/patch/467/raw/
Thanks,
Luc Verhaegen.
>From 34014b9884d43c48cf757b50fc64d6c4dcc3560f Mon Sep 17 00:00:00 2001
From: Luc Verhaegen
D
Idwer, please apply the ICH GPIO patch before applying this one.
Thanks,
Luc Verhaegen.
>From 4fa04184ae450493101bf274db7bb329298f1d14 Mon Sep 17 00:00:00 2001
From: Luc Verhaegen
Date: Sat, 24 Oct 2009 03:19:08 +0200
Subject: [PATCH] Board match for ASRock P4i65GV.
Same board enable as
On Sun, Oct 25, 2009 at 02:50:03AM +0200, Uwe Hermann wrote:
> On Sat, Oct 24, 2009 at 12:42:21AM +0200, Luc Verhaegen wrote:
> > > Let's use your original pci_dev_find variant and refactor it later.
>
> Yep.
>
> Acked-by: Uwe Hermann
>
>
On Sun, Oct 25, 2009 at 11:59:53AM +0100, Carl-Daniel Hailfinger wrote:
> On 25.10.2009 03:48, Luc Verhaegen wrote:
> > On Sun, Oct 25, 2009 at 02:50:03AM +0200, Uwe Hermann wrote:
> >
> >> On Sat, Oct 24, 2009 at 12:42:21AM +0200, Luc Verhaegen wrote:
> >>
rough everything yet again to
verify this.
Feel free to go and correct capitalisation. I'm off to do some real code
on unichrome.
Luc Verhaegen.
>From 8cefbb8aaa5c8a00dbce0ba90ab19e5b2822ee97 Mon Sep 17 00:00:00 2001
From: Luc Verhaegen
Date: Sun, 25 Oct 2009 18:58:01 +0100
Subject: [PATCH
On Wed, Oct 28, 2009 at 01:35:20AM +, Jonathan A. Kollasch wrote:
> On Wed, Oct 28, 2009 at 12:43:13AM +0100, Carl-Daniel Hailfinger wrote:
> > On 21.10.2009 23:33, Luc Verhaegen wrote:
> > > Board: Make Acorp 6A815EPD autodetectable.
> > >
> > > Add subsyst
utine. Are you sure that this code is really
necessary?
>From the lspci we can easily match several devices uniquely with
MSI:7120, not just the one.
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashrom.org
http://www.flashrom.org/mailman/listinfo/flashrom
On Wed, Nov 25, 2009 at 10:12:28AM -0800, Sean Nelson wrote:
> On 11/25/2009 10:01 AM, Sean Nelson wrote:
> >On 10/21/2009 4:44 PM, Luc Verhaegen wrote:
> >>On Sun, Oct 18, 2009 at 06:33:11PM -0700, Sean Nelson wrote:
> >>>the "anomaly" is the code for
Hi Jonathan,
I've swapped both id blocks around, so it could actually work this time
:)
Luc Verhaegen.
>From 518433bd67576fadce4f8f25399a61238dde5c7a Mon Sep 17 00:00:00 2001
From: Luc Verhaegen
Date: Sat, 28 Nov 2009 20:06:01 +0100
Subject: [PATCH] Board: Make Acorp 6A815EPD autode
Luc Verhaegen.
>From c801e537528ef4341724ca287db0fa5cea81b55f Mon Sep 17 00:00:00 2001
From: Luc Verhaegen
Date: Sat, 28 Nov 2009 21:15:24 +0100
Subject: [PATCH] Boards: Fix up MSI KT4V board enable.
* Add autodetection and remove match strings.
* Make use of vt823x_set_all_writes_to_
On Sat, Nov 28, 2009 at 12:21:50PM -0800, Sean Nelson wrote:
> On 11/28/2009 12:21 PM, Luc Verhaegen wrote:
> >Luc Verhaegen.
> >
> Acked-by: Sean Nelson
Thanks; -> r789.
Luc Verhaegen.
___
flashrom mailing list
flash
On Thu, Nov 19, 2009 at 05:53:51PM +0100, Carl-Daniel Hailfinger wrote:
> On 21.10.2009 17:53, Luc Verhaegen wrote:
> > On Tue, Oct 06, 2009 at 01:30:56PM +0200, Luc Verhaegen wrote:
> >
> >> Add chipset support for SiS963.
> >>
> >> Just touc
are 4 more which i would like
to see filled up in the next month.
The page where fosdem info will be kept for coreboot is:
http://www.coreboot.org/FOSDEM_2010
Hope to see many of you there!
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashr
people here feel about getting together with X.org folk
in some great restaurant with belgian cooking (le mirabelle) 500ms from
FOSDEM on saturday evening?
Luc Verhaegen
___
flashrom mailing list
flashrom@flashrom.org
http://www.flashrom.org/mailman/listinfo/flashrom
On Wed, Dec 02, 2009 at 01:13:18AM +0100, Carl-Daniel Hailfinger wrote:
> On 02.12.2009 00:36, Luc Verhaegen wrote:
> > The kind FOSDEM organizers have given us a DevRoom on saturday the 6th
> > of February, as requested.
> >
>
> Thanks a lot for organizing thi
t;failed.txt" (You can see here too:
> http://pastebin.com/f7056e678 )
>
> Thanks a lot! and... it is Phoenix BIOS!
No, it's an award, which always makes libv a happy camper :)
Give the attached patch a whirl. Raises what i think is GPIO2 on the
MCP SMBus.
If it works, please
27;t have a IRC chat program. That way, we can directly diagnose this
> with you.
>
>
> > I can see only now that I did not write the "v" on the command line,
> > dammit, please help needed.
> >
>
> Did you backup the old ima
fs51.htm#mainboardfs5
>
>
> Thanks and good luck,
> Emil
Emil, Carl-Daniel added a lot of SiS chipsets, is this report of yours
still valid on a more recent flashrom version?
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashrom.org
http://
ts/ProductsDetail.aspx?detailid=77&CategoryID=1&DetailName=Bios&MenuID=52&LanID=0
> http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=238&CategoryID=1&DetailName=Bios&MenuID=52&LanID=0
>
> Regards,
> Carl-Daniel
David,
Without the output
On Thu, Dec 03, 2009 at 12:46:39AM +0100, Luc Verhaegen wrote:
>
> David,
>
> Without the output of flashrom failing and an lspci -vvvnnxxx i will not
> even attempt looking at that bios.
>
> Please provide the requested info :)
>
> Luc Verhaegen.
Ah, ok, thi
y still need a copy of your
F-Segment:
dd if=/dev/mem of=/tmp/asus_m2n68_vm-f.rom bs=64k count=1 skip=15
Thanks,
Luc Verhaegen.
___
flashrom mailing list
flashrom@flashrom.org
http://www.flashrom.org/mailman/listinfo/flashrom
On Wed, Dec 02, 2009 at 11:09:04PM +, j...@settoplinux.org wrote:
>
> According to the wiki it looks like you want to get into bios security a bit.
> This may be an opritune time to introduce SerialICE???
If we can get Stepan to talk about it on FOSDEM, sure :)
Luc
On Thu, Dec 03, 2009 at 12:45:17AM +0100, Adrian Glaubitz wrote:
> Hi,
>
> On Thu, Dec 3, 2009 at 12:46 AM, Luc Verhaegen wrote:
> >> Please send the output of "flashrom -V", "lspci -nnvvvxxx", "superiotool
> >> -dV" and if tell us if
otocols: Non-SPI.
> Calibrating delay loop... OK.
> No EEPROM/flash device found.
>
> While the output of lspci is attached.
>
> HTH,
> Alessandro
Hi Alessandro,
Attached is a patch that might work for you.
Luc Verhaegen.
>From 53007dfa950fd75d705280b7e07452f0d2caa200 Mon
>From 9c6888f41dc6ede6d5f481a8bcb78c205d0ede67 Mon Sep 17 00:00:00 2001
From: Luc Verhaegen
Date: Thu, 3 Dec 2009 13:11:59 +0100
Subject: [PATCH] Boards: Add general nVidia MCP gpio routine.
Turns out that the AMD 8111 datasheet describes this bit of the MCP
perfectly.
Signed-off-by:
On Thu, Dec 03, 2009 at 01:18:54PM +0100, Carl-Daniel Hailfinger wrote:
> On 03.12.2009 13:18, Luc Verhaegen wrote:
> > Boards: Add general nVidia MCP gpio routine.
> >
> > Turns out that the AMD 8111 datasheet describes this bit of the MCP
> > perfectly.
> >
On Thu, Dec 03, 2009 at 08:50:12AM +0100, Alessandro Polverini wrote:
> Luc Verhaegen wrote:
> >On Wed, Oct 21, 2009 at 02:35:50PM +0200, Alessandro Polverini wrote:
> >
> >>Hello,
> >>this is the output of flashrom:
> >>
> >>flashrom v0.9.1-
enable hook under, i think, the trace is not
entirely clear, the following circumstances:
int15, ax=0xEBAC, bx=0xB000 (enable) bx=0xB001 (disable)
I will provide a possible board enable function soon.
Luc Verhaegen.
___
flashrom mailing list
nd to just go ahead and commit them after a bit of settling time.
Secondly, after that, the board matching will become a lot more strict.
If there is any subsystem id present, all subsystem ids will be used.
If one of the four subsystem ids is not null, all nulls have to be
matc
had some statement about this in the Random
> notes section. Please note that the wiki search on flashrom.org is
> non-functional right now. Hm. http://www.flashrom.org/Random_notes
> doesn't have this info.
>
> Idwer/Maciej, c
1 - 100 of 205 matches
Mail list logo
