This brings the requested modifications on top of version 9 of the
Cedrus VPU driver, that implements stateless video decoding using the
Request API.
Paul Kocialkowski (2):
media: cedrus: Fix error reporting in request validation
media: cedrus: Add TODO file with tasks to complete before
This fixes error reporting by using the appropriate logging helpers and
return codes, while introducing new messages when there are not enough
or too many buffers associated with the request.
Signed-off-by: Paul Kocialkowski
---
drivers/staging/media/sunxi/cedrus/cedrus.c | 15
When the elements listed are complete, the Cedrus driver will be ready
to move out of the staging area of the kernel.
Signed-off-by: Paul Kocialkowski
---
drivers/staging/media/sunxi/cedrus/TODO | 7 +++
1 file changed, 7 insertions(+)
create mode 100644 drivers/staging/media/sunxi/cedrus
Hi,
Le samedi 08 septembre 2018 à 13:24 +0200, Hans Verkuil a écrit :
> On 09/08/2018 12:22 PM, Chen-Yu Tsai wrote:
> > On Sat, Sep 8, 2018 at 6:06 PM Hans Verkuil wrote:
> > >
> > > On 09/07/2018 06:33 PM, Paul Kocialkowski wrote:
> > > > This bring
This fixes error reporting by using the appropriate logging helpers and
return codes, while introducing new messages when there are not enough
or too many buffers associated with the request.
Signed-off-by: Paul Kocialkowski
---
drivers/staging/media/sunxi/cedrus/cedrus.c | 15
following commit
is also required to select the sunxi SRAM driver:
* drivers: soc: Allow building the sunxi driver without ARCH_SUNXI
Paul Kocialkowski (4):
media: cedrus: Fix error reporting in request validation
media: cedrus: Add TODO file with tasks to complete before unstaging
media: cedrus
When the elements listed are complete, the Cedrus driver will be ready
to move out of the staging area of the kernel.
Signed-off-by: Paul Kocialkowski
---
drivers/staging/media/sunxi/cedrus/TODO | 7 +++
1 file changed, 7 insertions(+)
create mode 100644 drivers/staging/media/sunxi/cedrus
Since the sunxi SRAM driver is required to build the Cedrus driver,
select it in Kconfig.
Signed-off-by: Paul Kocialkowski
---
drivers/staging/media/sunxi/cedrus/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/staging/media/sunxi/cedrus/Kconfig
b/drivers/staging/media/sunxi
Since PHYS_PFN_OFFSET is not defined for all architectures, it is
requried to wrap it with ifdef so that it can be built on all
architectures.
Signed-off-by: Paul Kocialkowski
---
drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers
Hi,
Le dimanche 09 septembre 2018 à 11:04 +0200, Hans Verkuil a écrit :
> On 09/08/2018 09:42 PM, Paul Kocialkowski wrote:
> > Hi,
> >
> > Le samedi 08 septembre 2018 à 13:24 +0200, Hans Verkuil a écrit :
> > > On 09/08/2018 12:22 PM, Chen-Yu Tsai wrote:
> >
Hi,
Le lundi 10 septembre 2018 à 11:41 +0200, Hans Verkuil a écrit :
> On 09/07/2018 12:24 AM, Paul Kocialkowski wrote:
> > From: Paul Kocialkowski
> >
> > Stateless video decoding engines require both the MPEG-2 slices and
> > associated metadata from the video strea
result, remove the global IRQ spin lock.
Signed-off-by: Paul Kocialkowski
---
drivers/staging/media/sunxi/cedrus/cedrus.c | 1 -
drivers/staging/media/sunxi/cedrus/cedrus.h | 2 --
drivers/staging/media/sunxi/cedrus/cedrus_dec.c | 9 -
drivers/staging/media/sunxi/cedrus
This cosmetic change removes the heading 0 in the video-codec unit
address, as it's done for other nodes.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-a33.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm
there for this purpose) on the H3 and H5.
Some minor cosmetic fixes are also included regarding the video-codec
addresses in the device-tree.
Paul Kocialkowski (15):
ARM: dts: sun8i-a33: Remove heading 0 in video-codec unit address
ARM: dts: sun8i-h3: Remove heading 0 in video-codec unit
Add the H5-specific system control node description to its device-tree
with support for the SRAM C1 section, that will be used by the video
codec node later on.
Signed-off-by: Paul Kocialkowski
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 22
1 file changed, 22
.
Signed-off-by: Paul Kocialkowski
---
Documentation/devicetree/bindings/sram/sunxi-sram.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt
b/Documentation/devicetree/bindings/sram/sunxi-sram.txt
index 62dd0748f0ef..c043a6a4011e 100644
Now that we have specific nodes for the H3 and H5 system-controller
that allow proper access to the EMAC clock configuration register,
we no longer need a common dummy syscon node.
Switch the syscon label over to each platform's dtsi file.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boo
This cosmetic change removes the heading 0 in the video-codec unit
address, as it's done for other nodes.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boo
Add the description for the SRAM C1 section to the A64 device-tree.
Signed-off-by: Paul Kocialkowski
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts
Add the necessary compatible for supporting the H5 SoC along with a
description of the capabilities of this variant.
Signed-off-by: Paul Kocialkowski
---
drivers/staging/media/sunxi/cedrus/cedrus.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/staging/media/sunxi/cedrus
This introduces two new compatibles for the cedrus driver, for the
A64 and H5 platforms.
Signed-off-by: Paul Kocialkowski
---
Documentation/devicetree/bindings/media/cedrus.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/cedrus.txt
b
This adds the H5 SoC compatible to the list of device-tree matches for
the SRAM driver. Since the variant is the same as the A64 (that precedes
the H5), the same variant description is used.
Signed-off-by: Paul Kocialkowski
---
drivers/soc/sunxi/sunxi_sram.c | 4
1 file changed, 4
Add the necessary compatible for supporting the A64 SoC along with a
description of the capabilities of this variant.
Signed-off-by: Paul Kocialkowski
---
drivers/staging/media/sunxi/cedrus/cedrus.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/staging/media/sunxi/cedrus
-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 35d025af7deb..7157d954fb8c 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts
platform, but it seems safer that way.
Signed-off-by: Paul Kocialkowski
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 25
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index
This introduces a new compatible for the A64 SRAM C1 section, that is
compatible with the SRAM C1 section as found on the A10.
Signed-off-by: Paul Kocialkowski
---
Documentation/devicetree/bindings/sram/sunxi-sram.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree
.
Signed-off-by: Paul Kocialkowski
---
drivers/soc/sunxi/sunxi_sram.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
index b4b0f3480bd3..afa86b5506eb 100644
--- a/drivers/soc/sunxi/sunxi_sram.c
+++ b/drivers/soc
platform, but it seems safer that way.
Signed-off-by: Paul Kocialkowski
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25 +++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index
Hi,
Le vendredi 16 novembre 2018 à 17:47 +0800, Chen-Yu Tsai a écrit :
> On Fri, Nov 16, 2018 at 5:39 PM Maxime Ripard
> wrote:
> > On Thu, Nov 15, 2018 at 03:50:06PM +0100, Paul Kocialkowski wrote:
> > > Now that we have specific nodes for the H3 and H5 system-contro
Hi,
Le jeudi 15 novembre 2018 à 23:50 +0800, Chen-Yu Tsai a écrit :
> On Thu, Nov 15, 2018 at 10:50 PM Paul Kocialkowski
> wrote:
> > This cosmetic change removes the heading 0 in the video-codec unit
> > address, as it's done for other nodes.
> >
> > Signed-
Hi,
On Wed, 2018-10-10 at 17:33 +0900, Tomasz Figa wrote:
> Hi Paul,
>
> On Tue, Aug 28, 2018 at 5:02 PM Paul Kocialkowski
> wrote:
> > This introduces the required definitions for HEVC decoding support with
> > stateless VPUs. The controls associated to the HEVC slic
.
Cheers!
Paul Kocialkowski (2):
media: v4l: Add definitions for the HEVC slice format and controls
media: cedrus: Add HEVC/H.265 decoding support
Documentation/media/uapi/v4l/biblio.rst | 9 +
.../media/uapi/v4l/extended-controls.rst | 417 ++
.../media/uapi/v4l/pixfmt
, 4 bits.
Signed-off-by: Paul Kocialkowski
---
Documentation/media/uapi/v4l/biblio.rst | 9 +
.../media/uapi/v4l/extended-controls.rst | 417 ++
.../media/uapi/v4l/pixfmt-compressed.rst | 15 +
.../media/uapi/v4l/vidioc-queryctrl.rst | 18 +
.../media
This introduces support for HEVC/H.265 to the Cedrus VPU driver, with
both uni-directional and bi-directional prediction modes supported.
Field-coded (interlaced) pictures, custom quantization matrices and
10-bit output are not supported at this point.
Signed-off-by: Paul Kocialkowski
igned-off-by: Dan Carpenter
Acked-by: Paul Kocialkowski
Cheers,
Paul
> ---
> drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
> b/drivers/staging/media/
Hi,
On Fri, 2018-11-16 at 11:47 +0100, Maxime Ripard wrote:
> On Thu, Nov 15, 2018 at 03:39:55PM +0100, Paul Kocialkowski wrote:
> > We initially introduced a spin lock to ensure that the VPU registers
> > are not accessed concurrently between our setup function and IRQ
> >
for future codec support.
As a result, remove the global IRQ spin lock.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
Changes since v2:
* Rebased on top of the next media tree.
Changes since v1:
* Reworked commit message as suggested by Maxime.
drivers/staging/media/sunxi
Hi,
On Thu, 2018-11-15 at 23:35 +0800, Chen-Yu Tsai wrote:
> On Thu, Nov 15, 2018 at 10:51 PM Paul Kocialkowski
> wrote:
> > This adds nodes for the Video Engine and the associated reserved memory
> > for the H5. Up to 96 MiB of memory are dedicated to the CMA pool.
> >
Hi,
On Fri, 2018-11-30 at 11:38 +0800, Chen-Yu Tsai wrote:
> On Fri, Nov 16, 2018 at 12:52 AM Chen-Yu Tsai wrote:
> > On Thu, Nov 15, 2018 at 10:50 PM Paul Kocialkowski
> > wrote:
> > > Add the H5-specific system control node description to its device-tree
> >
-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-a33.dtsi | 15 ---
1 file changed, 15 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index c2c10cd4a210..9ac4fae6c10d 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts
Just like on the A33, the video engine on the H3 can map any address in
memory, so there is no particular need to have reserved memory at a fixed
address.
As a result, remove the reserved memory node and let the kernel allocate
the CMA pool wherever it sees fit.
Signed-off-by: Paul Kocialkowski
-off-by: Paul Kocialkowski
Acked-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index c2da3a3d373a..dbb7e71b6d69 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Chen-Yu Tsai
---
drivers/soc/sunxi/sunxi_sram.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
index 71e3ee4a3f19..fd81a3c0db45 100644
--- a/drivers/soc/sunxi
Add the necessary compatible for supporting the H5 SoC along with a
description of the capabilities of this variant.
Signed-off-by: Paul Kocialkowski
---
drivers/staging/media/sunxi/cedrus/cedrus.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/staging/media/sunxi/cedrus
Add the description for the SRAM C1 section to the A64 device-tree.
Since there is no entry for this section in the A64 manual, the base
address and size were only verified to be consistent empirically.
Signed-off-by: Paul Kocialkowski
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14
and H3;
* Corrected the SRAM bases and sizes to the best of our knowledge;
* Dropped cosmetic dt changes already included in the sunxi tree.
Paul Kocialkowski (15):
ARM: dts: sun8i: h3: Fix the system-control register range
ARM: dts: sun8i: a33: Remove unnecessary reserved memory node
ARM: dts
.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/sram/sunxi-sram.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt
b/Documentation/devicetree/bindings/sram/sunxi-sram.txt
index
This introduces a new compatible for the A64 SRAM C1 section, that is
compatible with the SRAM C1 section as found on the A10.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/sram/sunxi-sram.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a
This adds the Video Engine node for the A64. Since it can map the whole
DRAM range, there is no particular need for a reserved memory node
(unlike platforms preceding the A33).
Signed-off-by: Paul Kocialkowski
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 11 +++
1 file changed
This adds the H5 SoC compatible to the list of device-tree matches for
the SRAM driver. Since the variant is the same as the A64 (that precedes
the H5), the same variant description is used.
Signed-off-by: Paul Kocialkowski
---
drivers/soc/sunxi/sunxi_sram.c | 4
1 file changed, 4
This introduces two new compatibles for the cedrus driver, for the
A64 and H5 platforms.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/media/cedrus.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings
This adds the Video Engine node for the H5. Since it can map the whole
DRAM range, there is no particular need for a reserved memory node
(unlike platforms preceding the A33).
Signed-off-by: Paul Kocialkowski
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 11 +++
1 file changed, 11
.
Signed-off-by: Paul Kocialkowski
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 22
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index b41dc1aab67d..42bfb560b367 100644
--- a
driver use
the node corresponding to the proper SRAM driver (by switching the
syscon label over to each dtsi). This way, we no longer have two
separate nodes for the same register space.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
arch/arm/boot/dts/sunxi
Add the necessary compatible for supporting the A64 SoC along with a
description of the capabilities of this variant.
Signed-off-by: Paul Kocialkowski
---
drivers/staging/media/sunxi/cedrus/cedrus.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/staging/media/sunxi/cedrus
Hi,
On Wed, 2018-12-05 at 17:45 +0800, Chen-Yu Tsai wrote:
> On Wed, Dec 5, 2018 at 5:25 PM Paul Kocialkowski
> wrote:
> > Add the H5-specific system control node description to its device-tree
> > with support for the SRAM C1 section, that will be used by the video
>
Hi,
On Wed, 2018-12-05 at 17:49 +0800, Chen-Yu Tsai wrote:
> On Wed, Dec 5, 2018 at 5:48 PM Paul Kocialkowski
> wrote:
> > Hi,
> >
> > On Wed, 2018-12-05 at 17:45 +0800, Chen-Yu Tsai wrote:
> > > On Wed, Dec 5, 2018 at 5:25 PM Paul Kocialkowski
> > >
x27;. (kzalloc returns null)
>
> While here, remove the memset(), as kzalloc() already zeroes the
> struct.
Good catch, thanks for the patch!
> Signed-off-by: Mauro Carvalho Chehab
Acked-by: Paul Kocialkowski
> ---
> drivers/staging/media/sunxi/cedrus/cedrus.c | 3 ++-
ies:
>
> $ git grep -E "=\s*\{\s*\}"|wc -l
> 1951
>
> The standard-C compliant pattern has about 2500 entries:
>
> $ git grep -E "=\s*\{\s*NULL\s*\}"|wc -l
> 137
> $ git grep -E "=\s*\{\s*0\s*\}"|wc -l
>
Hi,
On Fri, 2018-12-07 at 22:22 +0100, Jernej Škrabec wrote:
> Hi!
>
> Dne sreda, 05. december 2018 ob 10:24:44 CET je Paul Kocialkowski napisal(a):
> > This adds the Video Engine node for the A64. Since it can map the whole
> > DRAM range, there is no particular need for a
Hi,
On Wed 26 May 21, 13:50, Hans Verkuil wrote:
> On 15/01/2021 21:01, Paul Kocialkowski wrote:
> > As some D-PHY controllers support both Rx and Tx mode, we need a way for
> > users to explicitly request one or the other. For instance, Rx mode can
> > be used along with MIP
Hi,
On Wed 26 May 21, 14:00, Hans Verkuil wrote:
> Hi Paul,
>
> On 15/01/2021 21:01, Paul Kocialkowski wrote:
> > This series introduces support for MIPI CSI-2, with the A31 controller that
> > is
> > found on most SoCs (A31, V3s and probably V5) as well as the A
Hi everyone,
On Fri 15 Jan 21, 21:01, Paul Kocialkowski wrote:
> As some D-PHY controllers support both Rx and Tx mode, we need a way for
> users to explicitly request one or the other. For instance, Rx mode can
> be used along with MIPI CSI-2 while Tx mode can be used with
(zero value) is kept to Tx so only the rkisp1 driver, which
uses D-PHY in Rx mode, needs to be adapted.
Signed-off-by: Paul Kocialkowski
---
drivers/staging/media/rkisp1/rkisp1-isp.c | 3 ++-
include/linux/phy/phy-mipi-dphy.h | 13 +
2 files changed, 15 insertions(+), 1
The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
is already supported and used for MIPI DSI this adds support for the
former, to be used with MIPI CSI-2.
This implementation is inspired by the Allwinner BSP implementation.
Signed-off-by: Paul Kocialkowski
---
drivers/phy
This allows selecting a dedicated CMA memory pool (specified via
device-tree) instead of the default one.
Signed-off-by: Paul Kocialkowski
---
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/media/platform/sunxi/sun6i-csi
same that already drives DSI, but used in Rx mode.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 50
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 07722bc5df11
one colorspace:raw
xfer:none ycbcr:601 quantization:full-range]
-> "sun6i-mipi-csi2":0 [ENABLED,IMMUTABLE]
Happy reviewing!
Paul Kocialkowski (14):
phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes
phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MI
MIPI CSI-2 is supported on the A83T with a dedicated controller that
covers both the protocol and D-PHY. It can be connected to the CSI
interface as a V4L2 subdev through the fwnode graph.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++
1
m the Allwinner BSP.
This version integrates MIPI CSI-2 support as a standalone V4L2 subdev
instead of merging it in the sun6i-csi driver.
It was tested on a Banana Pi M3 board with an OV8865 sensor in a 4-lane
configuration.
Signed-off-by: Paul Kocialkowski
---
drivers/media/platform/sunxi/Kc
This introduces YAML bindings documentation for the A83T MIPI CSI-2
controller.
Signed-off-by: Paul Kocialkowski
---
.../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 158 ++
1 file changed, 158 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/allwinner
the fwnode graph and
media controller API.
Signed-off-by: Paul Kocialkowski
---
drivers/media/platform/sunxi/Kconfig | 1 +
drivers/media/platform/sunxi/Makefile | 1 +
.../platform/sunxi/sun6i-mipi-csi2/Kconfig| 11 +
.../platform/sunxi/sun6i-mipi-csi2/Makefile | 4
controller doesn't have much to do itself except for selecting
the MIPI CSI-2 input.
Co-developed-by: Kévin L'hôpital
Signed-off-by: Kévin L'hôpital
Signed-off-by: Paul Kocialkowski
---
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 4
1 file changed, 4 insertions(+)
diff
Kévin L'hôpital
Signed-off-by: Paul Kocialkowski
---
.../platform/sunxi/sun6i-csi/sun6i_csi.c | 42 +++
1 file changed, 25 insertions(+), 17 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_c
using it for error reporting.
Signed-off-by: Paul Kocialkowski
---
.../sun8i_a83t_mipi_csi2.c| 40 ---
1 file changed, 40 deletions(-)
diff --git
a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c
b/drivers/media/platform/sunxi/sun8i
there.
Fixes: 5cc7522d8965 ("media: sun6i: Add support for Allwinner CSI V3s")
Co-developed-by: Kévin L'hôpital
Signed-off-by: Kévin L'hôpital
Signed-off-by: Paul Kocialkowski
---
.../platform/sunxi/sun6i-csi/sun6i_csi.h | 20 +--
1 file changed, 10 inserti
The V3s has a CSI0 camera controller which seems to be exclusively
dedicated to MIPI CSI-2, as it does not seem to have access to a
set of parallel input pins.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a
This introduces YAML bindings documentation for the A31 MIPI CSI-2
controller.
Signed-off-by: Paul Kocialkowski
---
.../media/allwinner,sun6i-a31-mipi-csi2.yaml | 168 ++
1 file changed, 168 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/allwinner
Hi Jernej,
On Fri 23 Oct 20, 20:18, Jernej Škrabec wrote:
> Dne petek, 23. oktober 2020 ob 19:45:33 CEST je Paul Kocialkowski napisal(a):
> > As some D-PHY controllers support both Rx and Tx mode, we need a way for
> > users to explicitly request one or the other. For instance, Rx
Hi,
On Mon 26 Oct 20, 16:38, Maxime Ripard wrote:
> On Fri, Oct 23, 2020 at 07:45:34PM +0200, Paul Kocialkowski wrote:
> > The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
> > is already supported and used for MIPI DSI this adds support for the
> > fo
Hi,
On Mon 26 Oct 20, 16:41, Maxime Ripard wrote:
> On Fri, Oct 23, 2020 at 07:45:35PM +0200, Paul Kocialkowski wrote:
> > This allows selecting a dedicated CMA memory pool (specified via
> > device-tree) instead of the default one.
> >
> > Signed-off-by: Paul Kocial
Hi,
On Mon 26 Oct 20, 17:00, Maxime Ripard wrote:
> On Fri, Oct 23, 2020 at 07:45:37PM +0200, Paul Kocialkowski wrote:
> > Bits related to the interface data width do not have any effect when
> > the CSI controller is taking input from the MIPI CSI-2 controller.
>
> I gues
Hi,
On Mon 26 Oct 20, 17:14, Maxime Ripard wrote:
> i2c? :)
Oops, good catch!
> On Fri, Oct 23, 2020 at 07:45:39PM +0200, Paul Kocialkowski wrote:
> > This introduces YAML bindings documentation for the A31 MIPI CSI-2
> > controller.
> >
> > Si
Hi,
On Mon 26 Oct 20, 17:56, Maxime Ripard wrote:
> On Fri, Oct 23, 2020 at 07:45:43PM +0200, Paul Kocialkowski wrote:
> > This introduces YAML bindings documentation for the A83T MIPI CSI-2
> > controller.
> >
> > Signed-off-by: Paul Kocialkowski
>
> What i
Hi,
On Mon 26 Oct 20, 18:00, Maxime Ripard wrote:
> On Fri, Oct 23, 2020 at 07:45:44PM +0200, Paul Kocialkowski wrote:
> > The A83T supports MIPI CSI-2 with a composite controller, covering both the
> > protocol logic and the D-PHY implementation. This controller seems to be
>
Hi,
On Tue 27 Oct 20, 19:44, Maxime Ripard wrote:
> On Tue, Oct 27, 2020 at 10:52:21AM +0100, Paul Kocialkowski wrote:
> > Hi,
> >
> > On Mon 26 Oct 20, 17:14, Maxime Ripard wrote:
> > > i2c? :)
> >
> > Oops, good catch!
> >
> > > On
Hi,
On Tue 27 Oct 20, 19:28, Maxime Ripard wrote:
>
> Hi,
>
> On Tue, Oct 27, 2020 at 10:23:26AM +0100, Paul Kocialkowski wrote:
> > On Mon 26 Oct 20, 16:38, Maxime Ripard wrote:
> > > On Fri, Oct 23, 2020 at 07:45:34PM +0200, Paul Kocialkowski wrote:
> > >
Hi Helen and thanks for the review,
On Fri 30 Oct 20, 19:44, Helen Koike wrote:
> On 10/23/20 2:45 PM, Paul Kocialkowski wrote:
> > The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
> > is already supported and used for MIPI DSI this adds support for the
&g
Hi Helen,
On Fri 30 Oct 20, 19:45, Helen Koike wrote:
> Hi Paul,
>
> On 10/23/20 2:45 PM, Paul Kocialkowski wrote:
> > Both 10 and 12-bit Bayer formats are stored aligned as 16-bit values
> > in memory, not unaligned 10 or 12 bits.
> >
> > Since the current co
Hi Helen,
On Fri 30 Oct 20, 19:44, Helen Koike wrote:
> Hi Paul,
>
> I have some comments through the series, I hope this helps.
Thanks for your comments :)
> On 10/23/20 2:45 PM, Paul Kocialkowski wrote:
> > This series introduces support for MIPI CSI-2, with the A31 contr
Hi again,
On Wed 04 Nov 20, 12:11, Paul Kocialkowski wrote:
> Hi Helen,
>
> On Fri 30 Oct 20, 19:44, Helen Koike wrote:
> > Hi Paul,
> >
> > I have some comments through the series, I hope this helps.
>
> Thanks for your comments :)
>
> > On
Hi,
On Mon 02 Nov 20, 10:21, Maxime Ripard wrote:
> On Fri, Oct 30, 2020 at 07:45:18PM -0300, Helen Koike wrote:
> > On 10/23/20 2:45 PM, Paul Kocialkowski wrote:
> > > The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 controller
> > > found on Allwinner SoCs
Hi,
On Mon 26 Oct 20, 17:54, Maxime Ripard wrote:
> On Fri, Oct 23, 2020 at 07:45:40PM +0200, Paul Kocialkowski wrote:
> > The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 controller
> > found on Allwinner SoCs such as the A31 and V3/V3s.
> >
> > It is a standal
Hi,
On Wed 04 Nov 20, 19:56, Maxime Ripard wrote:
> On Wed, Nov 04, 2020 at 12:34:58PM +0100, Paul Kocialkowski wrote:
> > > > + regmap_write(regmap, SUN6I_MIPI_CSI2_CFG_REG,
> > > > +SUN6I_M
Hi Sakari and thanks for the review!
On Thu 05 Nov 20, 10:45, Sakari Ailus wrote:
> On Fri, Oct 23, 2020 at 07:45:40PM +0200, Paul Kocialkowski wrote:
> > The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 controller
> > found on Allwinner SoCs such as the A31 and V3/V3s.
&
Hi,
On Wed 04 Nov 20, 13:36, Helen Koike wrote:
> Hi Paul,
>
> On 11/4/20 8:11 AM, Paul Kocialkowski wrote:
> > Hi Helen,
> >
> > On Fri 30 Oct 20, 19:44, Helen Koike wrote:
> >> Hi Paul,
> >>
> >> I have some comments through the series
Besides giving pointers to the relevant functions for PHY mode and
submode configuration, this clarifies the need to set them before
powering on the PHY.
Signed-off-by: Paul Kocialkowski
---
Documentation/driver-api/phy/phy.rst | 18 ++
1 file changed, 18 insertions(+)
diff
(zero value) is kept to Tx so only the rkisp1 driver, which
uses D-PHY in Rx mode, needs to be adapted.
Signed-off-by: Paul Kocialkowski
Acked-by: Helen Koike
---
drivers/staging/media/rkisp1/rkisp1-isp.c | 3 ++-
include/linux/phy/phy-mipi-dphy.h | 13 +
2 files changed
VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls (Input 0):
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
Total for sun6i-video device /dev/video0: 45, Succeeded: 45
block is
moved around before the interlaced conditional block for nicer code
symmetry (conditional blocks first) while at it.
Co-developed-by: Kévin L'hôpital
Signed-off-by: Kévin L'hôpital
Signed-off-by: Paul Kocialkowski
---
.../platform/sunxi/sun6i-csi/sun6i_csi.c
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