Document bindings for IMX8MQ VPU reset hardware block
Signed-off-by: Benjamin Gaignard
---
.../bindings/reset/fsl,imx8mq-vpu-reset.yaml | 54 +++
include/dt-bindings/reset/imx8mq-vpu-reset.h | 16 ++
2 files changed, 70 insertions(+)
create mode 100644
Documentation
as an independ reset
driver and to change the VPU driver to use it.
Benjamin Gaignard (4):
dt-bindings: reset: IMX8MQ VPU reset
reset: Add reset driver for IMX8MQ VPU block
media: hantro: Use reset driver
arm64: dts: imx8mq: Use reset driver for VPU hardware block
.../bindings/reset/fsl,i
Rather use a reset like feature inside the driver use the reset
controller API to get the same result.
Signed-off-by: Benjamin Gaignard
---
drivers/staging/media/hantro/Kconfig| 1 +
drivers/staging/media/hantro/imx8m_vpu_hw.c | 61 -
2 files changed, 12 insertions
Add a vpu reset hardware block node.
Signed-off-by: Benjamin Gaignard
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 31 ++-
1 file changed, 25 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
IMX8MQ SoC got a dedicated hardware block to reset the video processor
units (G1 and G2).
Signed-off-by: Benjamin Gaignard
---
drivers/reset/Kconfig| 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-imx8mq-vpu.c | 169 +++
3 files
Define allocation range for the default CMA region.
Signed-off-by: Benjamin Gaignard
Signed-off-by: Ezequiel Garcia
Signed-off-by: Adrian Ratiu
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale
re so can't
go into uapi structures. Compute the needed value is complex and require
information from the stream that only the userland knows so let it
provide the correct value to the driver.
Signed-off-by: Benjamin Gaignard
Signed-off-by: Ezequiel Garcia
Signed-off-by: Adrian Ratiu
---
drive
Add variant to IMX8M to enable G2/HEVC codec.
Define the capabilities for the hardware up to 3840x2160.
Retrieve the hardware version at init to distinguish G1 from G2.
Signed-off-by: Benjamin Gaignard
Signed-off-by: Ezequiel Garcia
Signed-off-by: Adrian Ratiu
---
drivers/staging/media/hantro
Le 17/02/2021 à 21:42, Ezequiel Garcia a écrit :
Hi Benjamin,
On Wed, 2021-02-17 at 09:02 +0100, Benjamin Gaignard wrote:
Add helper functions to allocate and free auxiliary buffers.
These buffers aren't for frames but are needed by the hardware
to store scaling matrix, tiles size, b
Document bindings for IMX8MQ VPU reset hardware block
Signed-off-by: Benjamin Gaignard
---
.../bindings/reset/fsl,imx8mq-vpu-reset.yaml | 54 +++
include/dt-bindings/reset/imx8mq-vpu-reset.h | 16 ++
2 files changed, 70 insertions(+)
create mode 100644
Documentation
breaks the compatibility between DTB and kernel but the driver
is still in staging directory and limited to IMX8MQ SoC.
Signed-off-by: Benjamin Gaignard
---
.../devicetree/bindings/media/nxp,imx8mq-vpu.yaml | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/Documentation/
IMX8MQ SoC got a dedicated hardware block to reset the video processor
units (G1 and G2).
Signed-off-by: Benjamin Gaignard
---
drivers/reset/Kconfig| 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-imx8mq-vpu.c | 169 +++
3 files
Rather use a reset like feature inside the driver use the reset
controller API to get the same result.
Signed-off-by: Benjamin Gaignard
---
drivers/staging/media/hantro/Kconfig| 1 +
drivers/staging/media/hantro/imx8m_vpu_hw.c | 61 -
2 files changed, 12 insertions
as an independ reset
driver and to change the VPU driver to use it.
Please note that this series break the compatibility between the DTB and
kernel. This break is limited to IMX8MQ SoC and is done when the driver
is still in staging directory.
version 2:
- Document the change in VPU bindings
Ben
Add a vpu reset hardware block node.
Signed-off-by: Benjamin Gaignard
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 31 ++-
1 file changed, 25 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
breaks the compatibility between DTB and kernel but the driver
is still in staging directory and limited to IMX8MQ SoC.
Signed-off-by: Benjamin Gaignard
---
version 3:
- Fix error in VPU example node
.../devicetree/bindings/media/nxp,imx8mq-vpu.yaml | 14 +-
1 file changed, 9 insert
IMX8MQ SoC got a dedicated hardware block to reset the video processor
units (G1 and G2).
Signed-off-by: Benjamin Gaignard
---
drivers/reset/Kconfig| 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-imx8mq-vpu.c | 169 +++
3 files
ion 2:
- Document the change in VPU bindings
Benjamin Gaignard (5):
dt-bindings: reset: IMX8MQ VPU reset
dt-bindings: media: IMX8MQ VPU: document reset usage
reset: Add reset driver for IMX8MQ VPU block
media: hantro: Use reset driver
arm64: dts: imx8mq: Use reset driver for VPU hardware
Document bindings for IMX8MQ VPU reset hardware block
Signed-off-by: Benjamin Gaignard
---
.../bindings/reset/fsl,imx8mq-vpu-reset.yaml | 54 +++
include/dt-bindings/reset/imx8mq-vpu-reset.h | 16 ++
2 files changed, 70 insertions(+)
create mode 100644
Documentation
Rather use a reset like feature inside the driver use the reset
controller API to get the same result.
Signed-off-by: Benjamin Gaignard
---
drivers/staging/media/hantro/Kconfig| 1 +
drivers/staging/media/hantro/imx8m_vpu_hw.c | 61 -
2 files changed, 12 insertions
Add a vpu reset hardware block node.
Signed-off-by: Benjamin Gaignard
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 31 ++-
1 file changed, 25 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
Le 03/03/2021 à 15:39, Philipp Zabel a écrit :
On Mon, 2021-03-01 at 16:17 +0100, Benjamin Gaignard wrote:
Rather use a reset like feature inside the driver use the reset
controller API to get the same result.
Signed-off-by: Benjamin Gaignard
---
drivers/staging/media/hantro/Kconfig
Le 03/03/2021 à 15:17, Philipp Zabel a écrit :
Hi Benjamin,
On Mon, 2021-03-01 at 16:17 +0100, Benjamin Gaignard wrote:
The two VPUs inside IMX8MQ share the same control block which can be see
as a reset hardware block.
This isn't a reset controller though. The control block also con
Le 03/03/2021 à 17:25, Philipp Zabel a écrit :
On Wed, 2021-03-03 at 16:20 +0100, Benjamin Gaignard wrote:
Le 03/03/2021 à 15:17, Philipp Zabel a écrit :
Hi Benjamin,
On Mon, 2021-03-01 at 16:17 +0100, Benjamin Gaignard wrote:
The two VPUs inside IMX8MQ share the same control block which
C_EXPBUF: OK
test Requests: OK
Total for hantro-vpu device /dev/video1: 46, Succeeded: 46, Failed: 0,
Warnings: 0
Grand Total for hantro-vpu device /dev/media1: 54, Succeeded: 54, Failed: 0,
Warnings: 0
Benjamin
Benjamin Gaignard (13):
dt-bindings: mfd: Add 'nxp,imx8mq-vpu-ctrl
Add 'nxp,imx8mq-vpu-ctrl' in the list of possible syscon.
It will used to access to the VPU control registers.
Signed-off-by: Benjamin Gaignard
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bi
compatible with older DT the driver is still capable to use 'ctrl'
reg-name even if it is deprecated now.
Signed-off-by: Benjamin Gaignard
---
version 5:
- This version doesn't break the backward compatibilty between kernel
and DT.
.../bindings/media/nxp,imx8mq-vpu.y
e a list of register
names so remove it.
Signed-off-by: Benjamin Gaignard
---
version 5:
- use syscon instead of VPU reset driver.
- if DT doesn't provide syscon keep backward compatibilty by using
'ctrl' reg-name.
drivers/staging/media/hantro/hantro.h | 5 +-
drivers/stagi
Add fields and flags as they are defined in
7.4.3.3.1 "General picture parameter set RBSP semantics of the
H.265 ITU specification.
Signed-off-by: Benjamin Gaignard
---
.../userspace-api/media/v4l/ext-ctrls-codec.rst| 14 ++
include/media/hevc-ct
Add decode params control and it associated structure to regroup
all the information that are needed to decode a reference frame as
it is describe in ITU-T Rec. H.265 section "8.3.2 Decoding process
for reference picture set".
Adapt Cedrus driver to these changes.
Signed-off-by
Change hantro_codec_ops run prototype from 'void' to 'int'.
This allow to cancel the job if an error occur while configuring
the hardware.
Signed-off-by: Benjamin Gaignard
---
version 5:
- forward hantro_h264_dec_prepare_run() return value in case
of error
drivers/
Define which HEVC profiles (up to level 5.1) and features
(no scaling, no 10 bits) are supported by the driver.
Signed-off-by: Benjamin Gaignard
---
drivers/staging/media/hantro/hantro.h | 3 ++
drivers/staging/media/hantro/hantro_drv.c | 58 +++
2 files changed, 61
If the variant doesn't offert postprocessed formats make sure it will
be ok.
Signed-off-by: Benjamin Gaignard
---
drivers/staging/media/hantro/hantro.h | 8 ++--
drivers/staging/media/hantro/hantro_postproc.c | 14 ++
drivers/staging/media/hantro/hantro_v4l2.c
The HEVC HANTRO driver needs to know the number of bits to skip at
the beginning of the slice header.
That is a hardware specific requirement so create a dedicated control
that this purpose.
Signed-off-by: Benjamin Gaignard
---
version 5:
- Be even more verbose in control documentation.
- Do
Make sure that V4L2_PIX_FMT_HEVC_SLICE is correctly handle by v4l2
of the driver.
Signed-off-by: Benjamin Gaignard
---
drivers/staging/media/hantro/hantro_v4l2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/staging/media/hantro/hantro_v4l2.c
b/drivers/staging/media/hantro
re so can't
go into uapi structures. Compute the needed value is complex and require
information from the stream that only the userland knows so let it
provide the correct value to the driver.
Signed-off-by: Benjamin Gaignard
Co-developed-by: Adrian Ratiu
Signed-off-by: Adrian Ratiu
Co-de
Add variant to IMX8M to enable G2/HEVC codec.
Define the capabilities for the hardware up to 3840x2160.
G2 doesn't have postprocessor, use the same clocks and got it
own interruption.
Signed-off-by: Benjamin Gaignard
---
version 5:
- remove useless postproc fields for G2
version 2:
- r
Split VPU node in two: one for G1 and one for G2 since they are
different hardware blocks.
Add syscon for hardware control block.
Remove reg-names property that is useless.
Each VPU node only need one interrupt.
Signed-off-by: Benjamin Gaignard
---
version 5:
- use syscon instead of VPU reset
Add 'nxp,imx8mq-vpu-ctrl' in the list of possible syscon.
It will used to access to the VPU control registers.
Signed-off-by: Benjamin Gaignard
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bi
compatible with older DT the driver is still capable to use 'ctrl'
reg-name even if it is deprecated now.
Signed-off-by: Benjamin Gaignard
---
version 5:
- This version doesn't break the backward compatibilty between kernel
and DT.
.../bindings/media/nxp,imx8mq-vpu.y
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK
Total for hantro-vpu device /dev/video1: 46, Succeeded: 46, Failed: 0,
Warnings: 0
Grand Total for hantro-vpu device /dev/media1: 54, Succeeded: 54, Failed: 0,
Warnings: 0
Benjamin
Benjamin Gai
e a list of register
names so remove it.
Signed-off-by: Benjamin Gaignard
---
version 5:
- use syscon instead of VPU reset driver.
- if DT doesn't provide syscon keep backward compatibilty by using
'ctrl' reg-name.
drivers/staging/media/hantro/hantro.h | 5 +-
drivers/stagi
Add fields and flags as they are defined in
7.4.3.3.1 "General picture parameter set RBSP semantics of the
H.265 ITU specification.
Signed-off-by: Benjamin Gaignard
---
.../userspace-api/media/v4l/ext-ctrls-codec.rst| 14 ++
include/media/hevc-ct
Add decode params control and it associated structure to regroup
all the information that are needed to decode a reference frame as
it is describe in ITU-T Rec. H.265 section "8.3.2 Decoding process
for reference picture set".
Adapt Cedrus driver to these changes.
Signed-off-by
Change hantro_codec_ops run prototype from 'void' to 'int'.
This allow to cancel the job if an error occur while configuring
the hardware.
Signed-off-by: Benjamin Gaignard
---
version 5:
- forward hantro_h264_dec_prepare_run() return value in case
of error
drivers/
Define which HEVC profiles (up to level 5.1) and features
(no scaling, no 10 bits) are supported by the driver.
Signed-off-by: Benjamin Gaignard
---
drivers/staging/media/hantro/hantro.h | 3 ++
drivers/staging/media/hantro/hantro_drv.c | 58 +++
2 files changed, 61
If the variant doesn't offert postprocessed formats make sure it will
be ok.
Signed-off-by: Benjamin Gaignard
---
drivers/staging/media/hantro/hantro.h | 8 ++--
drivers/staging/media/hantro/hantro_postproc.c | 14 ++
drivers/staging/media/hantro/hantro_v4l2.c
The HEVC HANTRO driver needs to know the number of bits to skip at
the beginning of the slice header.
That is a hardware specific requirement so create a dedicated control
that this purpose.
Signed-off-by: Benjamin Gaignard
---
version 5:
- Be even more verbose in control documentation.
- Do
Make sure that V4L2_PIX_FMT_HEVC_SLICE is correctly handle by v4l2
of the driver.
Signed-off-by: Benjamin Gaignard
---
drivers/staging/media/hantro/hantro_v4l2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/staging/media/hantro/hantro_v4l2.c
b/drivers/staging/media/hantro
Add variant to IMX8M to enable G2/HEVC codec.
Define the capabilities for the hardware up to 3840x2160.
G2 doesn't have postprocessor, use the same clocks and got it
own interruption.
Signed-off-by: Benjamin Gaignard
---
version 5:
- remove useless postproc fields for G2
version 2:
- r
re so can't
go into uapi structures. Compute the needed value is complex and require
information from the stream that only the userland knows so let it
provide the correct value to the driver.
Signed-off-by: Benjamin Gaignard
Co-developed-by: Adrian Ratiu
Signed-off-by: Adrian Ratiu
Co-de
Split VPU node in two: one for G1 and one for G2 since they are
different hardware blocks.
Add syscon for hardware control block.
Remove reg-names property that is useless.
Each VPU node only need one interrupt.
Signed-off-by: Benjamin Gaignard
---
version 5:
- use syscon instead of VPU reset
Le 26/03/2021 à 15:11, Philipp Zabel a écrit :
On Thu, Mar 18, 2021 at 09:20:35AM +0100, Benjamin Gaignard wrote:
Introducing G2 hevc video decoder lead to modify the bindings to allow
to get one node per VPUs.
VPUs share one hardware control block which is provided as a phandle on
an syscon
Le 26/03/2021 à 15:24, Philipp Zabel a écrit :
On Thu, Mar 18, 2021 at 09:20:46AM +0100, Benjamin Gaignard wrote:
Split VPU node in two: one for G1 and one for G2 since they are
different hardware blocks.
Add syscon for hardware control block.
Remove reg-names property that is useless.
Each
Add 'nxp,imx8mq-vpu-ctrl' in the list of possible syscon.
It will used to access to the VPU control registers.
Signed-off-by: Benjamin Gaignard
Acked-by: Rob Herring
---
version 7:
- Add Rob ack
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
1 file changed, 1 insertio
OK
test Requests: OK
Total for hantro-vpu device /dev/video1: 46, Succeeded: 46, Failed: 0,
Warnings: 0
Grand Total for hantro-vpu device /dev/media1: 54, Succeeded: 54, Failed: 0,
Warnings: 0
Benjamin
Benjamin Gaignard (13):
dt-bindings: mfd: Add 'nxp,imx8mq-vpu-ctrl' to sys
compatible with older DT the driver is still capable to use 'ctrl'
reg-name even if it is deprecated now.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Rob Herring
Reviewed-by: Philipp Zabel
---
version 7:
- Add Rob and Philipp reviewed-by tag
- Change syscon phandle name to nxp,imx8m-vpu-ct
e a list of register
names so remove it.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Philipp Zabel
---
version 7:
- Add Philipp reviewed-by tag.
- Change syscon phandle name.
version 5:
- use syscon instead of VPU reset driver.
- if DT doesn't provide syscon keep backward compatibilty by
Add fields and flags as they are defined in
7.4.3.3.1 "General picture parameter set RBSP semantics of the
H.265 ITU specification.
Signed-off-by: Benjamin Gaignard
---
.../userspace-api/media/v4l/ext-ctrls-codec.rst| 14 ++
include/media/hevc-ct
Add decode params control and it associated structure to regroup
all the information that are needed to decode a reference frame as
it is describe in ITU-T Rec. H.265 section "8.3.2 Decoding process
for reference picture set".
Adapt Cedrus driver to these changes.
Signed-off-by
Change hantro_codec_ops run prototype from 'void' to 'int'.
This allow to cancel the job if an error occur while configuring
the hardware.
Signed-off-by: Benjamin Gaignard
---
version 5:
- forward hantro_h264_dec_prepare_run() return value in case
of error
drivers/
Define which HEVC profiles (up to level 5.1) and features
(no scaling, no 10 bits) are supported by the driver.
Signed-off-by: Benjamin Gaignard
---
drivers/staging/media/hantro/hantro.h | 3 ++
drivers/staging/media/hantro/hantro_drv.c | 58 +++
2 files changed, 61
If the variant doesn't offert postprocessed formats make sure it will
be ok.
Signed-off-by: Benjamin Gaignard
---
drivers/staging/media/hantro/hantro.h | 8 ++--
drivers/staging/media/hantro/hantro_postproc.c | 14 ++
drivers/staging/media/hantro/hantro_v4l2.c
The HEVC HANTRO driver needs to know the number of bits to skip at
the beginning of the slice header.
That is a hardware specific requirement so create a dedicated control
that this purpose.
Signed-off-by: Benjamin Gaignard
---
version 5:
- Be even more verbose in control documentation.
- Do
Make sure that V4L2_PIX_FMT_HEVC_SLICE is correctly handle by v4l2
of the driver.
Signed-off-by: Benjamin Gaignard
---
drivers/staging/media/hantro/hantro_v4l2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/staging/media/hantro/hantro_v4l2.c
b/drivers/staging/media/hantro
Add variant to IMX8M to enable G2/HEVC codec.
Define the capabilities for the hardware up to 3840x2160.
G2 doesn't have postprocessor, use the same clocks and got it
own interruption.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Philipp Zabel
---
version 7:
- Add Philipp Reviewed-b
re so can't
go into uapi structures. Compute the needed value is complex and require
information from the stream that only the userland knows so let it
provide the correct value to the driver.
Signed-off-by: Benjamin Gaignard
Co-developed-by: Adrian Ratiu
Signed-off-by: Adrian Ratiu
Co-de
clocks need to assigned to make
sure that control block will be correctly clocked even if
only one device node is enabled.
Signed-off-by: Benjamin Gaignard
---
version 7:
- use nxp,imx8m-vpu-ctrl as phandle syscon property name
version 5:
- use syscon instead of VPU reset
arch/arm64/boot/dts
ideo1: 46, Succeeded: 46, Failed: 0,
Warnings: 0
Grand Total for hantro-vpu device /dev/media1: 54, Succeeded: 54, Failed: 0,
Warnings: 0
Benjamin
Benjamin Gaignard (13):
dt-bindings: mfd: Add 'nxp,imx8mq-vpu-ctrl' to syscon list
dt-bindings: media: nxp,imx8mq-vpu: Update the bindin
Add 'nxp,imx8mq-vpu-ctrl' in the list of possible syscon.
It will used to access to the VPU control registers.
Signed-off-by: Benjamin Gaignard
Acked-by: Rob Herring
Acked-by: Lee Jones
---
version 8:
- Add Lee ack
version 7:
- Add Rob ack
Documentation/devicetree/bindings/mfd/s
compatible with older DT the driver is still capable to use 'ctrl'
reg-name even if it is deprecated now.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Rob Herring
Reviewed-by: Philipp Zabel
---
version 7:
- Add Rob and Philipp reviewed-by tag
- Change syscon phandle name to nxp,imx8m-vpu-ct
Add fields and flags as they are defined in
7.4.3.3.1 "General picture parameter set RBSP semantics of the
H.265 ITU specification.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
version 8:
- add Ezequiel review tag
.../userspace-api/media/v4l/ext-ctrls-codec.rst
e a list of register
names so remove it.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Philipp Zabel
---
version 7:
- Add Philipp reviewed-by tag.
- Change syscon phandle name.
version 5:
- use syscon instead of VPU reset driver.
- if DT doesn't provide syscon keep backward compatibilty by
Add decode params control and it associated structure to regroup
all the information that are needed to decode a reference frame as
it is describe in ITU-T Rec. H.265 section "8.3.2 Decoding process
for reference picture set".
Adapt Cedrus driver to these changes.
Signed-off-by
Change hantro_codec_ops run prototype from 'void' to 'int'.
This allow to cancel the job if an error occur while configuring
the hardware.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
version 8:
- add Ezequiel review tag
version 5:
- forward hantro_
Define which HEVC profiles (up to level 5.1) and features
(no scaling, no 10 bits) are supported by the driver.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
version 8:
- add Ezequiel review tag
drivers/staging/media/hantro/hantro.h | 3 ++
drivers/staging/media
If the variant doesn't offert postprocessed formats make sure it will
be ok.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
version 8:
- add Ezequiel review tag
drivers/staging/media/hantro/hantro.h | 8 ++--
drivers/staging/media/hantro/hantro_postp
The HEVC HANTRO driver needs to know the number of bits to skip at
the beginning of the slice header.
That is a hardware specific requirement so create a dedicated control
that this purpose.
Signed-off-by: Benjamin Gaignard
---
version 5:
- Be even more verbose in control documentation.
- Do
Make sure that V4L2_PIX_FMT_HEVC_SLICE is correctly handle by v4l2
of the driver.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
version 8:
- Add Ezequiel review tag
drivers/staging/media/hantro/hantro_v4l2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers
Add variant to IMX8M to enable G2/HEVC codec.
Define the capabilities for the hardware up to 3840x2160.
G2 doesn't have postprocessor, use the same clocks and got it
own interruption.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Philipp Zabel
Reviewed-by: Ezequiel Garcia
---
version 8:
re so can't
go into uapi structures. Compute the needed value is complex and require
information from the stream that only the userland knows so let it
provide the correct value to the driver.
Signed-off-by: Benjamin Gaignard
Co-developed-by: Adrian Ratiu
Signed-off-by: Adrian Ratiu
Co-de
clocks need to assigned to make
sure that control block will be correctly clocked even if
only one device node is enabled.
Signed-off-by: Benjamin Gaignard
---
version 7:
- use nxp,imx8m-vpu-ctrl as phandle syscon property name
version 5:
- use syscon instead of VPU reset
arch/arm64/boot/dts
Add 'nxp,imx8mq-vpu-ctrl' to the list of possible syscon.
It will used to access the VPU control registers.
Signed-off-by: Benjamin Gaignard
Acked-by: Rob Herring
Acked-by: Lee Jones
---
version 9:
- corrections in commit message
version 8:
- Add Lee ack
version 7:
- A
compatible with older DT the driver is still capable to use the 'ctrl'
reg-name even if it is deprecated now.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Rob Herring
Reviewed-by: Philipp Zabel
---
version 9:
- Corrections in commit message
version 7:
- Add Rob and Philipp revie
edia1: 54, Succeeded: 54, Failed: 0,
Warnings: 0
Benjamin
Benjamin Gaignard (13):
dt-bindings: mfd: Add 'nxp,imx8mq-vpu-ctrl' to syscon list
dt-bindings: media: nxp,imx8mq-vpu: Update the bindings for G2 support
media: hantro: Use syscon instead of 'ctrl' register
e a list of register
names so remove it.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Philipp Zabel
---
version 9:
- Corrections in commit message
version 7:
- Add Philipp reviewed-by tag.
- Change syscon phandle name.
version 5:
- use syscon instead of VPU reset driver.
- if DT doesn&#
Add fields and flags as they are defined in
7.4.3.3.1 "General picture parameter set RBSP semantics of the
H.265 ITU specification.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
version 8:
- add Ezequiel review tag
.../userspace-api/media/v4l/ext-ctrls-codec.rst
Change hantro_codec_ops run prototype from 'void' to 'int'.
This allows the driver to cancel the job if an error occurs while configuring
the hardware.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
version 9:
- Corrections in commit message
versio
Add decode params control and the associated structure to group
all the information that are needed to decode a reference frame as
is described in ITU-T Rec. H.265 section "8.3.2 Decoding process
for reference picture set".
Adapt Cedrus driver to these changes.
Signed-off-by: Benjami
Define which HEVC profiles (up to level 5.1) and features
(no scaling, no 10 bits) are supported by the driver.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
version 8:
- add Ezequiel review tag
drivers/staging/media/hantro/hantro.h | 3 ++
drivers/staging/media
If the variant doesn't support postprocessed formats make sure it will
be ok.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
version 9:
- Corrections in commit message
version 8:
- add Ezequiel review tag
drivers/staging/media/hantro/hantro.h
Make sure that V4L2_PIX_FMT_HEVC_SLICE is correctly handled by the driver.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
version 9:
- Corrections in commit message
version 8:
- Add Ezequiel review tag
drivers/staging/media/hantro/hantro_v4l2.c | 1 +
1 file changed, 1
The HEVC HANTRO driver needs to know the number of bits to skip at
the beginning of the slice header.
That is a hardware specific requirement so create a dedicated control
for this purpose.
Signed-off-by: Benjamin Gaignard
---
version 9:
- Corrections in commit message.
- Move control
re so can't
go into uapi structures. Computing the needed value is complex and requires
information from the stream that only the userland knows so let it
provide the correct value to the driver.
Signed-off-by: Benjamin Gaignard
Co-developed-by: Adrian Ratiu
Signed-off-by: Adrian Ratiu
Co
Add variant to IMX8M to enable G2/HEVC codec.
Define the capabilities for the hardware up to 3840x2160.
G2 doesn't have a postprocessor, uses the same clocks and has it
own interrupt.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Philipp Zabel
Reviewed-by: Ezequiel Garcia
---
vers
the clocks need to be assigned to make
sure that the control block will be correctly clocked even if
only one device node is enabled.
Signed-off-by: Benjamin Gaignard
---
version 9:
- Corrections in commit message
version 7:
- use nxp,imx8m-vpu-ctrl as phandle syscon property name
version 5
Le 16/04/2021 à 12:54, Lucas Stach a écrit :
Am Mittwoch, dem 07.04.2021 um 09:35 +0200 schrieb Benjamin Gaignard:
In order to be able to share the control hardware block between
VPUs use a syscon instead a ioremap it in the driver.
To keep the compatibility with older DT if 'nxp,imx8m
Le 16/04/2021 à 17:14, Lucas Stach a écrit :
Am Freitag, dem 16.04.2021 um 15:08 +0200 schrieb Benjamin Gaignard:
Le 16/04/2021 à 12:54, Lucas Stach a écrit :
Am Mittwoch, dem 07.04.2021 um 09:35 +0200 schrieb Benjamin Gaignard:
In order to be able to share the control hardware block between
Le 20/04/2021 à 11:16, Hans Verkuil a écrit :
On 20/04/2021 11:10, Benjamin Gaignard wrote:
Le 16/04/2021 à 17:14, Lucas Stach a écrit :
Am Freitag, dem 16.04.2021 um 15:08 +0200 schrieb Benjamin Gaignard:
Le 16/04/2021 à 12:54, Lucas Stach a écrit :
Am Mittwoch, dem 07.04.2021 um 09:35
pect mime since it is confusing
- remove useless clocks in VPUs nodes
Benjamin Gaignard (9):
media: hevc: Add fields and flags for hevc PPS
media: hevc: Add decode params control
media: hantro: change hantro_codec_ops run prototype to return errors
media: hantro: Define HEVC codec profile
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