On Thu, Mar 18, 2021 at 09:20:35AM +0100, Benjamin Gaignard wrote:
> Introducing G2 hevc video decoder lead to modify the bindings to allow
> to get one node per VPUs.
> VPUs share one hardware control block which is provided as a phandle on
> an syscon.
> Each node got now one reg and one interrup
On Thu, Mar 18, 2021 at 09:20:36AM +0100, Benjamin Gaignard wrote:
> In order to be able to share the control hardware block between
> VPUs use a syscon instead a ioremap it in the driver.
> To keep the compatibility with older DT if 'nxp,imx8mq-vpu-ctrl'
> phandle is not found look at 'ctrl' reg-n
On Thu, Mar 18, 2021 at 09:20:45AM +0100, Benjamin Gaignard wrote:
> Add variant to IMX8M to enable G2/HEVC codec.
> Define the capabilities for the hardware up to 3840x2160.
> G2 doesn't have postprocessor, use the same clocks and got it
> own interruption.
>
> Signed-off-by: Benjamin Gaignard
On Thu, Mar 18, 2021 at 09:20:46AM +0100, Benjamin Gaignard wrote:
> Split VPU node in two: one for G1 and one for G2 since they are
> different hardware blocks.
> Add syscon for hardware control block.
> Remove reg-names property that is useless.
> Each VPU node only need one interrupt.
>
> Signe
Le 26/03/2021 à 15:11, Philipp Zabel a écrit :
On Thu, Mar 18, 2021 at 09:20:35AM +0100, Benjamin Gaignard wrote:
Introducing G2 hevc video decoder lead to modify the bindings to allow
to get one node per VPUs.
VPUs share one hardware control block which is provided as a phandle on
an syscon.
E
Le 26/03/2021 à 15:24, Philipp Zabel a écrit :
On Thu, Mar 18, 2021 at 09:20:46AM +0100, Benjamin Gaignard wrote:
Split VPU node in two: one for G1 and one for G2 since they are
different hardware blocks.
Add syscon for hardware control block.
Remove reg-names property that is useless.
Each VPU
On Fri, Mar 26, 2021 at 03:26:15PM +0100, Benjamin Gaignard wrote:
>
> Le 26/03/2021 à 15:11, Philipp Zabel a écrit :
> > On Thu, Mar 18, 2021 at 09:20:35AM +0100, Benjamin Gaignard wrote:
> > > Introducing G2 hevc video decoder lead to modify the bindings to allow
> > > to get one node per VPUs.
On Fri, 2021-03-26 at 15:33 +0100, Benjamin Gaignard wrote:
>
> Le 26/03/2021 à 15:24, Philipp Zabel a écrit :
> > On Thu, Mar 18, 2021 at 09:20:46AM +0100, Benjamin Gaignard wrote:
> > > Split VPU node in two: one for G1 and one for G2 since they are
> > > different hardware blocks.
> > > Add sys
327
x86_64 randconfig-a006-20210327
x86_64 randconfig-a001-20210327
x86_64 randconfig-a004-20210327
x86_64 randconfig-a005-20210327
i386 randconfig-a004-20210326
i386 randconfig-a003-20210326
i386 randconfig-a00
x86_64 randconfig-a004-20210327
x86_64 randconfig-a005-20210327
i386 randconfig-a004-20210326
i386 randconfig-a003-20210326
i386 randconfig-a001-20210326
i386 randconfig-a002-20210326
i386
-20210326
i386 randconfig-a003-20210326
i386 randconfig-a001-20210326
i386 randconfig-a002-20210326
i386 randconfig-a006-20210326
i386 randconfig-a005-20210326
x86_64 randconfig-a012-20210326
x86_64
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