Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> Adds device tree binding documentation for clocks in the
> MT7621 SOC.
>
> Signed-off-by: Sergio Paracuellos
> ---
> .../bindings/clock/mediatek,mt7621-clk.yaml | 67 +++
> 1 file changed, 67 insertions(+)
> create mode 100644
Quoting Sergio Paracuellos (2020-11-22 01:55:53)
> The documentation for this SOC only talks about two
> registers regarding to the clocks:
> * SYSC_REG_CPLL_CLKCFG0 - provides some information about
> boostrapped refclock. PLL and dividers used for CPU and some
> sort of BUS.
> * SYSC_REG_CPLL_CLK
Hi Stephen,
Thanks for the review.
On Thu, Dec 17, 2020 at 10:09 AM Stephen Boyd wrote:
>
> Quoting Sergio Paracuellos (2020-11-22 01:55:53)
> > The documentation for this SOC only talks about two
> > registers regarding to the clocks:
> > * SYSC_REG_CPLL_CLKCFG0 - provides some information abou
Hi Stephen,
Thanks for the review!
On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd wrote:
>
> Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > Adds device tree binding documentation for clocks in the
> > MT7621 SOC.
> >
> > Signed-off-by: Sergio Paracuellos
> > ---
> > .../bindings/clock/medi
Quoting Sergio Paracuellos (2020-12-17 02:01:39)
>
> On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd wrote:
> >
> > Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> >
> > > diff --git
> > > a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > > b/Documentation/devicetree/bindin
Quoting Sergio Paracuellos (2020-12-17 01:54:18)
>
> On Thu, Dec 17, 2020 at 10:09 AM Stephen Boyd wrote:
> >
> > Quoting Sergio Paracuellos (2020-11-22 01:55:53)
> > > diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
> > > new file mode 100644
> > > index ..cf6f
There are certain conditional expressions in rtl8192e, where a boolean
variable is compared with true/false, in forms such as (foo == true) or
(false != bar), which does not comply with checkpatch.pl (CHECK:
BOOL_COMPARISON), according to which boolean variables should be
themselves used in the con
On Thu, Dec 17, 2020 at 2:58 AM Stephen Boyd wrote:
>
> Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > Adds device tree binding documentation for clocks in the
> > MT7621 SOC.
> >
> > Signed-off-by: Sergio Paracuellos
> > ---
> > .../bindings/clock/mediatek,mt7621-clk.yaml | 67 +
Hi Rob,
On Thu, Dec 17, 2020 at 4:05 PM Rob Herring wrote:
>
> On Thu, Dec 17, 2020 at 2:58 AM Stephen Boyd wrote:
> >
> > Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > > Adds device tree binding documentation for clocks in the
> > > MT7621 SOC.
> > >
> > > Signed-off-by: Sergio Paracuell
Power domain fits much better than a voltage regulator in regards to
a proper hardware description and from a software perspective as well.
Hence replace the core regulator with the power domain. Note that this
doesn't affect any existing DTBs because we haven't started to use the
regulator yet, an
Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs, which reduces
power consumption and heating of the Tegra chips. Tegra SoC has multiple
hardware units which belong to a core power domain of the SoC and share
the core voltage. The voltage must be selected in accordance to a minimum
require
Power domain fits much better than a voltage regulator in regards to
a proper hardware description and from a software perspective as well.
Hence replace the core regulator with the power domain. Note that this
doesn't affect any existing DTBs because we haven't started to use the
regulator yet, an
Document new DVFS OPP table and power domain properties of the video
decoder engine.
Signed-off-by: Dmitry Osipenko
---
.../devicetree/bindings/media/nvidia,tegra-vde.txt | 12
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.
Power domain fits much better than a voltage regulator in regards to
a proper hardware description and from a software perspective as well.
Hence replace the core regulator with the power domain. Note that this
doesn't affect any existing DTBs because we haven't started to use the
regulator yet, an
All NVIDIA Tegra SoCs have a core power domain where majority of hardware
blocks reside. Add binding for the core power domain.
Signed-off-by: Dmitry Osipenko
---
.../arm/tegra/nvidia,tegra20-core-domain.yaml | 48 +++
1 file changed, 48 insertions(+)
create mode 100644
Documen
Add dev_pm_opp_set_voltage() which allows OPP table users to set voltage
in accordance to a given OPP. In particular this is needed for driving
voltage of a generic power domain which uses OPPs and doesn't have a
clock.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 52 +
Add dev_pm_opp_get_required_pstate() which allows OPP users to retrieve
required performance state of a given OPP.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 22 ++
include/linux/pm_opp.h | 10 ++
2 files changed, 32 insertions(+)
diff --git a/driver
Extend OPP API with dev_pm_opp_sync_regulators() function, which syncs
voltage state of regulators.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 42 ++
include/linux/pm_opp.h | 11 +++
2 files changed, 53 insertions(+)
diff --git a/
Document new DVFS OPP table and power domain properties of the Host1x bus
and devices sitting on the bus.
Signed-off-by: Dmitry Osipenko
---
.../display/tegra/nvidia,tegra20-host1x.txt | 49 +++
1 file changed, 49 insertions(+)
diff --git
a/Documentation/devicetree/bindings/d
A required OPP may not be available, and thus, all OPPs which are using
this required OPP should be unavailable too.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index
Make regulator_sync_voltage() to re-balance voltage state of a coupled
regulators instead of changing the voltage directly.
Signed-off-by: Dmitry Osipenko
---
drivers/regulator/core.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
in
Fix adding OPP entries in a wrong (opposite) order if OPP rate is
unavailable. The OPP comparison is erroneously skipped if OPP rate is
missing, thus OPPs are left unsorted.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 23 ---
drivers/opp/opp.h | 2 +-
2 files ch
Document "clocks" sub-node which describes Tegra SoC clocks that require
a higher voltage of the core power domain in order to operate properly on
a higher rates.
Signed-off-by: Dmitry Osipenko
---
.../bindings/clock/nvidia,tegra20-car.txt | 26 +++
.../bindings/clock/nvidia,
Add "performance" column to debug summary which shows performance state
of all power domains and theirs devices.
Signed-off-by: Dmitry Osipenko
---
drivers/base/power/domain.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/base/power/domain.c
Add a ceil version of the dev_pm_opp_find_level(). It's handy to have if
levels don't start from 0 in OPP table and zero usually means a minimal
level.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 49 ++
include/linux/pm_opp.h | 8 +++
The GR3D1 hardware unit needs to pulse hardware reset after removing power
clamp, otherwise reset won't be deasserted. Hence give reset a pulse after
removing the clamp. This stayed unnoticed previously because power
management wasn't supported by the 3D driver until recently and all power
gates ar
The tegra_powergate_power_up() has a typo in the error code path where it
will try to disable clocks twice, fix it. In practice that error never
happens, so this is a minor correction.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-
Make set_performance_state() callback optional in order to remove the
need from power domain drivers to implement a dummy callback. If callback
isn't implemented by a GENPD driver, then the performance state is passed
to the parent domain.
Signed-off-by: Dmitry Osipenko
---
drivers/base/power/do
Switch all clocks of a power domain to a safe rate which is suitable
for all possible voltages in order to ensure that hardware constraints
aren't violated when power domain state toggles.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 92 -
Add new Kconfig SOC_TEGRA_COMMON option which selects configuration
options that are common for all Tegra SoCs. Select PM_OPP by default
since from now on OPPs will be used by Tegra drivers which present on
all SoC generations, like display controller driver for example.
Signed-off-by: Dmitry Osip
Print out domain name when reset fails to acquire for debugging purposes
and to make formatting of GENPD errors consistent in the driver.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/tegra/pmc.c b/dri
Fix voltage coupler lockup which happens when voltage-spread is out
of range due to a bug in the code. The max-spread requirement shall be
accounted when CPU regulator doesn't have consumers. This problem is
observed on Tegra30 Ouya game console once system-wide DVFS is enabled
in a device-tree.
F
NVIDIA Tegra SoCs have a power domains topology such that child domains
only clamp a power rail, while parent domain controls shared performance
state of the multiple child domains. In this case child's domain doesn't
need to have OPP table. Hence we want to allow children power domains to
pass per
The Core domain is a parent of PMC power domains, hence PMC domains
should be set up as a sub-domains of the parent (Core) domain if
"power-domains" phandle presents in a device-tree node of PMC domain.
This allows to propagate GENPD performance changes to the parent Core
domain if performance cha
Add host1x_channel_stop() which waits till channel becomes idle and then
stops the channel hardware. This is needed for supporting suspend/resume
by host1x drivers since the hardware state is lost after power-gating,
thus the channel needs to be stopped before entering into suspend.
Signed-off-by:
Add OPP and PM support to the GR2D driver. This is required for enabling
system-wide DVFS and supporting dynamic power management using a generic
power domain.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr2d.c | 73
Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table
initialization.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra20-emc.c | 57 +++---
1 file changed, 4 insertions(+), 53 deletions(-)
diff --git a/drivers/memory/tegra/tegra20-emc.c
b
Allow lower core voltages on Acer A500.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
in
Add resource-managed versions of OPP API functions. This removes a need
from drivers to store and manage OPP table pointers.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 173 +
drivers/opp/of.c | 25 ++
include/linux/pm_opp.h | 5
Host1x channel should be idling before hardware is turned off, hence
stop the channel in the suspend callback.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/vic.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/v
Support set_opp() customization without requiring to use regulators. This
is needed by drivers which want to use dev_pm_opp_set_rate() for changing
rates of a multiple clocks and don't need to touch regulator.
One example is NVIDIA Tegra30/114 SoCs which have two sibling 3D hardware
units which sh
Enable CPU voltage scaling and thermal throttling on Tegra20 Ventana board.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-ventana.dts | 40 ++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts
b/arch/arm/b
Add OPP and SoC core voltage scaling support to the display controller
driver. This is required for enabling system-wide DVFS on pre-Tegra186
SoCs.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/dc.c | 66 ++
The debug message always prints rate=0 instead of a proper value, fix it.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/of.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/opp/of.c b/drivers/opp/of.c
index 3b5a4c8bc62f..1f2038a4420b 100644
--- a/drivers/opp/of.c
Add OPP tables and power domains to Tegra30 device-tree.
Signed-off-by: Dmitry Osipenko
---
.../tegra30-asus-nexus7-grouper-common.dtsi |4 +
arch/arm/boot/dts/tegra30-beaver.dts |4 +
arch/arm/boot/dts/tegra30-cardhu.dtsi | 20 +-
arch/arm/boot/dts/tegra30-colibri.d
Print OPP level in debug message of _opp_add_static_v2(). This helps to
chase GENPD bugs.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/of.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/opp/of.c b/drivers/opp/of.c
index 1f2038a4420b..56b153ea5c56 100644
--- a
Add OPP tables and power domains to the Tegra20 device-tree.
Signed-off-by: Dmitry Osipenko
---
.../boot/dts/tegra20-acer-a500-picasso.dts| 4 +
arch/arm/boot/dts/tegra20-colibri.dtsi| 6 +-
arch/arm/boot/dts/tegra20-harmony.dts | 6 +-
arch/arm/boot/dts/tegra20-paz00.d
NVIDIA Tegra SoCs have multiple power domains, each domain corresponds
to an external SoC power rail. Core power domain covers vast majority of
hardware blocks within a Tegra SoC. The voltage of a power domain should
be set to a value which satisfies all devices within a power domain. Add
driver fo
The device-tree compatibles are swapped in the code, correct them.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr2d.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tegra/gr2d.c b/drivers/gpu
Add common helper which initializes OPP table for Tegra SoC core devices.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/common.c | 137 +
include/soc/tegra/common.h | 35 ++
2 files changed, 172 insertions(+)
diff --git a/drivers/soc/tegra/com
The core voltage shall not drop until state of Core domain is synced,
i.e. all device drivers that use Core domain are loaded and ready.
Support Core domain state syncing. The Core domain driver invokes the
core-regulator voltage syncing once the state of domain is synced, at
this point the Core v
Add suspend/resume and generic power domain support to the Host1x driver.
This is required for enabling system-wide DVFS and supporting dynamic
power management using a generic power domain.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/host1x/
Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table
initialization.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra30-emc.c | 57 +++---
1 file changed, 4 insertions(+), 53 deletions(-)
diff --git a/drivers/memory/tegra/tegra30-emc.c
b
Add OPP and add PM support to the GR3D driver. This is required for
enabling system-wide DVFS and supporting dynamic power management using
a generic power domain.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr3d.c | 264 +++
Add OPP and generic power domain support to the video decoder driver.
This allows us to utilize a modern GENPD API for newer device-trees and
support DVFS of the decoder hardware. Note that older DTBs will continue
to work like they did it before this patch.
Tested-by: Peter Geis
Tested-by: Nicol
Allow lower core voltages on Ventana board.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-ventana.dts | 32 ---
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts
b/arch/arm/boot/dts/tegra20-ventana.dts
ind
Enable CPU voltage scaling and thermal throttling on Tegra30 Cardhu board.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30-cardhu.dtsi | 61 ++-
1 file changed, 60 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi
b/arch/arm/bo
The Clock-and-Reset controller resides in a "core" power domain on
NVIDIA Tegra SoCs. In order to support voltage scaling of the core power
rail, we need to hook up some clocks (which can't operate properly on a
lower voltages above certain clock rates) to the core power domain in
order to ensure t
On 17/12/2020 19:06, Dmitry Osipenko wrote:
> Enable CPU voltage scaling and thermal throttling on Tegra20 Ventana board.
>
> Signed-off-by: Dmitry Osipenko
> ---
> arch/arm/boot/dts/tegra20-ventana.dts | 40 ++-
> 1 file changed, 39 insertions(+), 1 deletion(-)
>
> diff
On 17/12/2020 19:06, Dmitry Osipenko wrote:
> Enable CPU voltage scaling and thermal throttling on Tegra30 Cardhu board.
>
> Signed-off-by: Dmitry Osipenko
> ---
Same comments as 47/48
> arch/arm/boot/dts/tegra30-cardhu.dtsi | 61 ++-
> 1 file changed, 60 insertions(+
17.12.2020 21:21, Mikko Perttunen пишет:
> On 12/17/20 8:06 PM, Dmitry Osipenko wrote:
>> Add suspend/resume and generic power domain support to the Host1x driver.
>> This is required for enabling system-wide DVFS and supporting dynamic
>> power management using a generic power domain.
>>
>> Tested
On 12/17/20 8:06 PM, Dmitry Osipenko wrote:
Add suspend/resume and generic power domain support to the Host1x driver.
This is required for enabling system-wide DVFS and supporting dynamic
power management using a generic power domain.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off
17.12.2020 21:28, Daniel Lezcano пишет:
> On 17/12/2020 19:06, Dmitry Osipenko wrote:
>> Enable CPU voltage scaling and thermal throttling on Tegra20 Ventana board.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>> arch/arm/boot/dts/tegra20-ventana.dts | 40 ++-
>> 1 file cha
On 17/12/2020 20:01, Dmitry Osipenko wrote:
> 17.12.2020 21:28, Daniel Lezcano пишет:
>> On 17/12/2020 19:06, Dmitry Osipenko wrote:
>>> Enable CPU voltage scaling and thermal throttling on Tegra20 Ventana board.
>>>
>>> Signed-off-by: Dmitry Osipenko
>>> ---
>>> arch/arm/boot/dts/tegra20-ventana
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a003-20201217
x86_64 randconfig-a006-20201217
x86_64 randconfig-a002-20201217
x86_64 randconfig-a005-20201217
x86_64
17.12.2020 22:36, Daniel Lezcano пишет:
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&trip
17.12.2020 21:45, Dmitry Osipenko пишет:
> 17.12.2020 21:21, Mikko Perttunen пишет:
>> On 12/17/20 8:06 PM, Dmitry Osipenko wrote:
>>> Add suspend/resume and generic power domain support to the Host1x driver.
>>> This is required for enabling system-wide DVFS and supporting dynamic
>>> power manage
On 17/12/2020 21:28, Dmitry Osipenko wrote:
> 17.12.2020 22:36, Daniel Lezcano пишет:
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
>
18.12.2020 00:19, Daniel Lezcano пишет:
> On 17/12/2020 21:28, Dmitry Osipenko wrote:
>> 17.12.2020 22:36, Daniel Lezcano пишет:
>> +type = "critical";
>> +};
>> +};
>> +
>> +
Fixed a coding style issue.
Signed-off-by: Daniel West
---
drivers/staging/most/video/video.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/most/video/video.c
b/drivers/staging/most/video/video.c
index 829df899b993..c58192ab0c2a 100644
--- a/drivers/sta
On Thu, 2020-12-17 at 15:45 -0800, Daniel West wrote:
> Fixed a coding style issue.
It may pass checkpatch without warning, but it's uncommon kernel coding style.
> diff --git a/drivers/staging/most/video/video.c
> b/drivers/staging/most/video/video.c
[]
> @@ -365,8 +365,8 @@ static const struct
On 17-12-20, 21:05, Dmitry Osipenko wrote:
> Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs, which reduces
> power consumption and heating of the Tegra chips. Tegra SoC has multiple
> hardware units which belong to a core power domain of the SoC and share
> the core voltage. The voltage
From: Zhaoyang Huang
Add SLAB_RECLAIM_ACCOUNT to ashmem_range cache since it has registered
shrinker, which make memAvailable more presiced.
Signed-off-by: Zhaoyang Huang
---
drivers/staging/android/ashmem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/an
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