[PATCH v2 01/19] docs: phy: Add a part about PHY mode and submode

Besides giving pointers to the relevant functions for PHY mode and submode configuration, this clarifies the need to set them before powering on the PHY. Signed-off-by: Paul Kocialkowski --- Documentation/driver-api/phy/phy.rst | 18 ++ 1 file changed, 18 insertions(+) diff --gi

[PATCH v2 02/19] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes

As some D-PHY controllers support both Rx and Tx mode, we need a way for users to explicitly request one or the other. For instance, Rx mode can be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI. Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY. The default

[PATCH v2 00/19] Allwinner MIPI CSI-2 support for A31/V3s/A83T

This series introduces support for MIPI CSI-2, with the A31 controller that is found on most SoCs (A31, V3s and probably V5) as well as the A83T-specific controller. While the former uses the same MIPI D-PHY that is already supported for DSI, the latter embeds its own D-PHY. In order to distinguis

[PATCH v2 05/19] media: sun6i-csi: Only configure the interface data width for parallel

Bits related to the interface data width are only applicable to the parallel interface and are irrelevant when the CSI controller is taking input from the MIPI CSI-2 controller. In prevision of adding support for this case, set these bits conditionally so there is no ambiguity. The conditional blo

[PATCH v2 06/19] dt-bindings: media: sun6i-a31-csi: Add MIPI CSI-2 input port

The A31 CSI controller supports two distinct input interfaces: parallel and an external MIPI CSI-2 bridge. The parallel interface is often connected to a set of hardware pins while the MIPI CSI-2 bridge is an internal FIFO-ish link. As a result, these two inputs are distinguished as two different p

[PATCH v2 03/19] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2

The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter is already supported and used for MIPI DSI this adds support for the former, to be used with MIPI CSI-2. This implementation is inspired by Allwinner's V3s Linux SDK implementation, which was used as a documentation base. Sig

[PATCH v2 07/19] media: sun6i-csi: Add support for MIPI CSI-2 bridge input

The A31 CSI controller supports a MIPI CSI-2 bridge input, which has its own dedicated port in the fwnode graph. Support for this input is added with this change: - two pads are defined for the media entity instead of one and only one needs to be connected at a time; - the pads currently match t

[PATCH v2 04/19] media: sun6i-csi: Use common V4L2 format info for storage bpp

V4L2 has a common helper which can be used for calculating the number of stored bits per pixels of a given (stored) image format. Use the helper-returned structure instead of our own switch/case list. Note that a few formats are not in that list so we keep them as special cases. The custom switch

[PATCH v2 09/19] ARM: dts: sunxi: h3/h5: Add CSI controller port for parallel input

Since the CSI controller binding is getting a bit more complex due to the addition of MIPI CSI-2 bridge support, make the ports node explicit with the parallel port. This way, it's clear that the controller only supports parallel interface input and there's no confusion about the port number. Sig

[PATCH v2 10/19] ARM: dts: sun8i: v3s: Add CSI1 controller port for parallel input

Since the CSI controller binding is getting a bit more complex due to the addition of MIPI CSI-2 bridge support, make the ports node explicit with the parallel port. This way, it's clear that the controller only supports parallel interface input and there's no confusion about the port number. Sig

[PATCH v2 08/19] ARM: dts: sun8i: a83t: Add CSI controller ports

Since the CSI controller binding is getting a bit more complex due to the addition of MIPI CSI-2 bridge support, make the ports node explicit with the parallel and MIPI CSI-2 bridge ports. This way, it's clear that the controller supports both parallel and MIPI CSI-2 interface inputs and there's n

[PATCH v2 12/19] dt-bindings: media: Add A31 MIPI CSI-2 bindings documentation

This introduces YAML bindings documentation for the A31 MIPI CSI-2 controller. Signed-off-by: Paul Kocialkowski --- .../media/allwinner,sun6i-a31-mipi-csi2.yaml | 151 ++ 1 file changed, 151 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/allwinner,sun

[PATCH v2 14/19] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support

MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge controller. The controller uses a separate D-PHY, which is the same that is otherwise used for MIPI DSI, but used in Rx mode. On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does not have access to any parallel

[PATCH v2 13/19] media: sunxi: Add support for the A31 MIPI CSI-2 controller

The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge found on Allwinner SoCs such as the A31 and V3/V3s. It is a standalone block, connected to the CSI controller on one side and to the MIPI D-PHY block on the other. It has a dedicated address space, interrupt line and clock. It is repr

[PATCH v2 15/19] MAINTAINERS: Add entry for the Allwinner A31 MIPI CSI-2 bridge

Add myself as maintainer of the A31 MIPI CSI-2 bridge media driver. Signed-off-by: Paul Kocialkowski --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0644128640fb..a1352171778b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -709,6 +709,14

[PATCH v2 11/19] arm64: dts: allwinner: a64: Add CSI controller port for parallel input

Since the CSI controller binding is getting a bit more complex due to the addition of MIPI CSI-2 bridge support, make the ports node explicit with the parallel port. This way, it's clear that the controller only supports parallel interface input and there's no confusion about the port number. Sig

[PATCH v2 19/19] MAINTAINERS: Add entry for the Allwinner A83T MIPI CSI-2 bridge

Add myself as maintainer of the A83T MIPI CSI-2 bridge media driver. Signed-off-by: Paul Kocialkowski --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a1352171778b..3b48612657b6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -717,6 +717,1

[PATCH v2 16/19] dt-bindings: media: Add A83T MIPI CSI-2 bindings documentation

This introduces YAML bindings documentation for the A83T MIPI CSI-2 controller. Signed-off-by: Paul Kocialkowski --- .../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 147 ++ 1 file changed, 147 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/allwinner,su

[PATCH v2 18/19] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node

MIPI CSI-2 is supported on the A83T with a dedicated controller that covers both the protocol and D-PHY. It can be connected to the CSI interface as a V4L2 subdev through the fwnode graph. This is not done by default since connecting the bridge without a subdev attached to it will cause a failure

[PATCH v2 17/19] media: sunxi: Add support for the A83T MIPI CSI-2 controller

The A83T supports MIPI CSI-2 with a composite controller, covering both the protocol logic and the D-PHY implementation. This controller seems to be found on the A83T only and probably was abandoned since. This implementation splits the protocol and D-PHY registers and uses the PHY framework inter