On Tue, Nov 10, 2020 at 09:29:45PM +0100, Thierry Reding wrote:
> > + err = dev_pm_opp_of_add_table(dc->dev);
> > + if (err) {
> > + dev_err(dc->dev, "failed to add OPP table: %d\n", err);
> > + goto put_hw;
> > + }
> > +
> > + err = devm_add_action(dc->dev, tegra_dc_dei
On Sun, 8 Nov 2020 at 13:19, Dmitry Osipenko wrote:
>
> 05.11.2020 18:22, Dmitry Osipenko пишет:
> > 05.11.2020 12:45, Ulf Hansson пишет:
> > ...
> >> I need some more time to review this, but just a quick check found a
> >> few potential issues...
> >
> > Thank you for starting the review! I'm pr
On Thu, 5 Nov 2020 at 00:44, Dmitry Osipenko wrote:
>
> Document new DVFS OPP table and voltage regulator properties of the
> Host1x bus and devices sitting on the bus.
>
> Signed-off-by: Dmitry Osipenko
> ---
> .../display/tegra/nvidia,tegra20-host1x.txt | 56 +++
> 1 file cha
On Wed, Nov 11, 2020 at 12:23:41AM +0300, Dmitry Osipenko wrote:
> 10.11.2020 23:32, Mark Brown пишет:
> >>> + if (!device_property_present(dc->dev, "core-supply"))
> >>> + return;
> >> This is a potentially heavy operation, so I think we should avoid that
> >> here. How about you use dev
Good morning,
I am writing again to inform you that I am yet to receives your email
correspondent concerning the previous email I sent to you. Please let me know
if you will be able to sale the product's to my director directly. Could you
kindly reply, is urgent for business.
Re
Good morning,
I am writing again to inform you that I am yet to receives your email
correspondent concerning the previous email I sent to you. Please let me know
if you will be able to sale the product's to my director directly. Could you
kindly reply, is urgent for business.
Re
On 06/11/2020 16:14, Maxime Ripard wrote:
> Hi,
>
> Here's an attempt to removing the dma_direct_set_offset calls we have in
> numerous drivers and move all those quirks into a global notifier as suggested
> by Robin.
For patches 4-7:
Acked-by: Hans Verkuil
It's fine by me if this series is me
Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for new mt7621-pll and mt7621-clk
and update the rest of the nodes to use them.
Signed-off-by: Sergio Paracuellos
---
drivers/s
For a long time the mt7621 uses a fixed cpu clock which causes a problem
if the cpu frequency is not 880MHz.
This patch adds cpu/ahb/apb clock calculation code and binds clocks to
mt7621-pll node.
Adapted from OpenWrt:
c7ca224299 ramips: fix cpu clock of mt7621 and add dt clk devices
Signed-off-b
Adds dt binding header for 'mediatek,mt7621-pll' PLL controller
and for 'mediatek,mt7621-clk' clock gates.
Signed-off-by: Sergio Paracuellos
---
include/dt-bindings/clock/mt7621-clk.h | 39 ++
1 file changed, 39 insertions(+)
create mode 100644 include/dt-bindings/clock/
Adds device tree binding documentation for clock gates in the
MT7621 SOC.
Signed-off-by: Sergio Paracuellos
---
.../bindings/clock/mediatek,mt7621-clk.yaml | 52 +++
1 file changed, 52 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/mediatek,mt7621-cl
Adds device tree binding documentation for PLL controller in
the MT7621 SOC.
Signed-off-by: Sergio Paracuellos
---
.../bindings/clock/mediatek,mt7621-pll.yaml | 51 +++
1 file changed, 51 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/mediatek,mt7621
Adding myself as maintainer for mt7621 clock driver.
Signed-off-by: Sergio Paracuellos
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f1f088a29bc2..c34c12d62355 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11142,6 +11142,14 @@ L:
In mt7621 SoC register 'SYSC_REG_CPLL_CLKCFG1' allows to
handle a bunch of gates to enable/disable clocks for
all or some ip cores. Add a driver to properly handle them.
Parent clocks for this gates are not documented at all in
the SoC documentation so all of them have been assumed looking
into th
This patchset ports CPU clock detection for MT7621 from OpenWrt
and adds a complete clock plan for the mt7621 SOC.
The documentation for this SOC only talks about two registers
regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped
refclock. PLL and dividers
Hi!
On Thu, Nov 12, 2020 at 12:30 AM Sergio Paracuellos
wrote:
>
> This patchset ports CPU clock detection for MT7621 from OpenWrt
> and adds a complete clock plan for the mt7621 SOC.
>
> The documentation for this SOC only talks about two registers
> regarding to the clocks:
> * SYSC_REG_CPLL_CL
On Thu, Nov 12, 2020 at 9:26 AM Chuanhong Guo wrote:
>
> I've already said in previous threads that clock assignment in
> current linux kernel is not trustworthy.
> I've got the clock plan for mt7621 now. (Can't share it, sorry.)
> Most of your clock assumptions above are incorrect.
> I've made a
Hi Nicolas,
On Wed, Nov 04, 2020 at 11:39:33AM +0100, Nicolas Saenz Julienne wrote:
> Use devm_rpi_firmware_get() so as to make sure we release RPi's firmware
> interface when unbinding the device.
Unless I am mistaken this driver does not really need the firmware
structure past rpi_ts_probe(), a
Hi Chuanhong,
On Thu, Nov 12, 2020 at 2:26 AM Chuanhong Guo wrote:
[snip]
>
> I've already said in previous threads that clock assignment in
> current linux kernel is not trustworthy.
> I've got the clock plan for mt7621 now. (Can't share it, sorry.)
> Most of your clock assumptions above are inc
Hi,
On Thu, Nov 12, 2020 at 2:34 AM Chuanhong Guo wrote:
>
> On Thu, Nov 12, 2020 at 9:26 AM Chuanhong Guo wrote:
> >
> > I've already said in previous threads that clock assignment in
> > current linux kernel is not trustworthy.
> > I've got the clock plan for mt7621 now. (Can't share it, sorry
gasket_interrupt_set_eventfd() misses to call eventfd_ctx_put() in an
error path. We check interrupt is valid before calling
eventfd_ctx_fdget() to fix it.
There is the same issue in gasket_interrupt_clear_eventfd(), Add the
missed function call to fix it.
Fixes: 9a69f5087ccc ("drivers/staging: G
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