Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

Hi! On Sun, Aug 18, 2019 at 5:51 PM Oleksij Rempel wrote: > > lets see more code: > drivers/staging/mt7621-mmc/sd.c > /* clock source for host: global */ > #if defined(CONFIG_SOC_MT7620) > static u32 hclks[] = {4800}; /* +/- by chhung */ > #elif defined(CONFIG_SOC_MT7621) > static u32 hclks[]

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

Am 18.08.19 um 10:44 schrieb Chuanhong Guo: > On Sun, Aug 18, 2019 at 4:26 PM Chuanhong Guo wrote: >> >> Hi! >> >> On Sun, Aug 18, 2019 at 3:59 PM Oleksij Rempel >> wrote: >>> >>> Am 18.08.19 um 09:19 schrieb Chuanhong Guo: Hi! On Sun, Aug 18, 2019 at 2:10 PM Oleksij Rempel

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

On Sun, Aug 18, 2019 at 4:26 PM Chuanhong Guo wrote: > > Hi! > > On Sun, Aug 18, 2019 at 3:59 PM Oleksij Rempel wrote: > > > > Am 18.08.19 um 09:19 schrieb Chuanhong Guo: > > > Hi! > > > > > > On Sun, Aug 18, 2019 at 2:10 PM Oleksij Rempel > > > wrote: > > >> > > We have at least 2 know re

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

Hi! On Sun, Aug 18, 2019 at 3:59 PM Oleksij Rempel wrote: > > Am 18.08.19 um 09:19 schrieb Chuanhong Guo: > > Hi! > > > > On Sun, Aug 18, 2019 at 2:10 PM Oleksij Rempel > > wrote: > >> > We have at least 2 know registers: > SYSC_REG_CPLL_CLKCFG0 - it provides some information about bo

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

Am 18.08.19 um 09:19 schrieb Chuanhong Guo: > Hi! > > On Sun, Aug 18, 2019 at 2:10 PM Oleksij Rempel wrote: >> We have at least 2 know registers: SYSC_REG_CPLL_CLKCFG0 - it provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS (AHB?

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

Hi! On Sun, Aug 18, 2019 at 2:10 PM Oleksij Rempel wrote: > > >> We have at least 2 know registers: > >> SYSC_REG_CPLL_CLKCFG0 - it provides some information about boostrapped > >> refclock. PLL and dividers used for CPU and some sort of BUS (AHB?). > >> SYSC_REG_CPLL_CLKCFG1 - a banch of gates t

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

Am 18.08.19 um 04:29 schrieb Chuanhong Guo: > Hi! > > On Sun, Aug 18, 2019 at 2:06 AM Oleksij Rempel wrote: SYSC_REG_CPLL_CLKCFG1 register is a clock gate controller. It is used to enable or disable clocks. Jist wild assumption. All peripheral devices are suing bus clock. >>> >>> T

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

Hi! On Sun, Aug 18, 2019 at 2:06 AM Oleksij Rempel wrote: > >> SYSC_REG_CPLL_CLKCFG1 register is a clock gate controller. It is used to > >> enable or disable clocks. > >> Jist wild assumption. All peripheral devices are suing bus clock. > > > > This assumption is incorrect. When this patchset i

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

Am 17.08.19 um 18:22 schrieb Chuanhong Guo: > Hi! > > On Sat, Aug 17, 2019 at 11:40 PM Oleksij Rempel wrote: > >> In provided link [0] the ralink_clk_init function is reading >> SYSC_REG_CPLL_CLKCFG0 R/W register. >> This register is used to determine clock source, clock freq and CPU or bus >>

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

Hi! On Sat, Aug 17, 2019 at 11:40 PM Oleksij Rempel wrote: > In provided link [0] the ralink_clk_init function is reading > SYSC_REG_CPLL_CLKCFG0 R/W register. > This register is used to determine clock source, clock freq and CPU or bus > clocks. This register should only be changed by boot

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

Hi, Am 17.08.19 um 16:42 schrieb Chuanhong Guo: Hi! On Tue, Aug 13, 2019 at 11:51 PM Rob Herring wrote: [...] +Example: + pll { + compatible = "mediatek,mt7621-pll"; You didn't answer Stephen's question on v1. I thought he was asking why there's a syscon in compatible str

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

Hi, Am 17.08.19 um 16:42 schrieb Chuanhong Guo: Hi! On Tue, Aug 13, 2019 at 11:51 PM Rob Herring wrote: [...] +Example: + pll { + compatible = "mediatek,mt7621-pll"; You didn't answer Stephen's question on v1. I thought he was asking why there's a syscon in compatible str

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

Hi! On Tue, Aug 13, 2019 at 11:51 PM Rob Herring wrote: > [...] > > +Example: > > + pll { > > + compatible = "mediatek,mt7621-pll"; > > You didn't answer Stephen's question on v1. I thought he was asking why there's a syscon in compatible string. I noticed that the syscon in my p

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

On Wed, Jul 24, 2019 at 10:23:08AM +0800, Chuanhong Guo wrote: > This commit adds device tree binding documentation for MT7621 > PLL controller. > > Signed-off-by: Chuanhong Guo > --- > > Change since v1: > drop useless syscon in compatible string > > .../bindings/clock/mediatek,mt7621-pll.txt

Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

Hi Chuanhong, On Wed, Jul 24, 2019 at 10:23:08AM +0800, Chuanhong Guo wrote: > This commit adds device tree binding documentation for MT7621 > PLL controller. > > Signed-off-by: Chuanhong Guo > --- > > Change since v1: > drop useless syscon in compatible string > > .../bindings/clock/mediatek