Hi Dan,
On Mon, Nov 30, 2020 at 1:15 PM Dan Carpenter wrote:
>
> On Thu, Nov 19, 2020 at 07:05:22AM +0100, Sergio Paracuellos wrote:
> > > > +static inline void phy_write(struct mt7621_pci_phy *phy, u32 val, u32
> > > > reg)
> > > > +{
> > > > + regmap_write(phy->regmap, reg, val);
> > >
> >
Hi Vinod,
On Mon, Nov 30, 2020 at 11:48 AM Vinod Koul wrote:
>
> On 21-11-20, 16:50, Sergio Paracuellos wrote:
> > This series adds support for the PCIe PHY found in the Mediatek
> > MT7621 SoC.
> >
> > There is also a 'mt7621-pci' driver which is the controller part
> > which is still in staging
On Thu, Nov 19, 2020 at 07:05:22AM +0100, Sergio Paracuellos wrote:
> > > +static inline void phy_write(struct mt7621_pci_phy *phy, u32 val, u32
> > > reg)
> > > +{
> > > + regmap_write(phy->regmap, reg, val);
> >
> > Why not use regmap_ calls directly and avoid the dummy wrappers..?
>
> This
On 21-11-20, 16:50, Sergio Paracuellos wrote:
> This series adds support for the PCIe PHY found in the Mediatek
> MT7621 SoC.
>
> There is also a 'mt7621-pci' driver which is the controller part
> which is still in staging and is a client of this phy.
>
> Both drivers have been tested together in
MASK(7, 6)
+
+#define MAX_PHYS 2
+
+/**
+ * struct mt7621_pci_phy - Mt7621 Pcie PHY core
+ * @dev: pointer to device
+ * @regmap: kernel regmap pointer
+ * @phy: pointer to the kernel PHY device
+ * @port_base: base register
+ * @has_dual_port: if the phy has dual ports.
+ * @bypass_pipe_rst: mark if
get_resource' instead of 'of_address_to_resource'.
Changes in v2:
- Reorder patches to get bindings first in the series.
- Don't use child nodes in the device tree. Use #phy-cells=1 instead.
- Update driver code with new 'xlate' function for the new device tree.
-
Add bindings to describe Mediatek MT7621 PCIe PHY.
Signed-off-by: Sergio Paracuellos
Reviewed-by: Rob Herring
---
.../bindings/phy/mediatek,mt7621-pci-phy.yaml | 36 +++
1 file changed, 36 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/mediatek,mt7621
On 20-11-20, 17:20, Sergio Paracuellos wrote:
> Hi Vinod,
>
> On Thu, Nov 19, 2020 at 4:43 PM Sergio Paracuellos
> wrote:
> >
> > This series adds support for the PCIe PHY found in the Mediatek
> > MT7621 SoC.
> >
> > There is also a 'mt7621-pci' driver which is the controller part
> > which is s
stead.
> - Update driver code with new 'xlate' function for the new device tree.
> - Minor changes in driver's macros changing some spaces to tabs.
>
> Thanks in advance for your time.
>
> Best regards,
> Sergio Paracuellos
>
> [0]:
> http://driverdev
0x7
+
+#define MAX_PHYS 2
+
+/**
+ * struct mt7621_pci_phy - Mt7621 Pcie PHY core
+ * @dev: pointer to device
+ * @regmap: kernel regmap pointer
+ * @phy: pointer to the kernel PHY device
+ * @port_base: base register
+ * @has_dual_port: if the phy has dual ports.
+ * @bypass_pipe_rst: mark if &#
Add bindings to describe Mediatek MT7621 PCIe PHY.
Signed-off-by: Sergio Paracuellos
Reviewed-by: Rob Herring
---
.../bindings/phy/mediatek,mt7621-pci-phy.yaml | 36 +++
1 file changed, 36 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/mediatek,mt7621
ad.
- Update driver code with new 'xlate' function for the new device tree.
- Minor changes in driver's macros changing some spaces to tabs.
Thanks in advance for your time.
Best regards,
Sergio Paracuellos
[0]:
http://driverdev.linuxdriverproject.org/pipermail/driverdev-dev
Hi Vinod,
Thanks for the review.
On Thu, Nov 19, 2020 at 6:31 AM Vinod Koul wrote:
>
> On 31-10-20, 13:22, Sergio Paracuellos wrote:
>
> > +#define RG_PE1_PIPE_REG 0x02c
> > +#define RG_PE1_PIPE_RST BIT(12)
> > +#define RG_PE1_PIPE_CMD_FR
On 31-10-20, 13:22, Sergio Paracuellos wrote:
> +#define RG_PE1_PIPE_REG 0x02c
> +#define RG_PE1_PIPE_RST BIT(12)
> +#define RG_PE1_PIPE_CMD_FRC BIT(4)
> +
> +#define RG_P0_TO_P1_WIDTH0x100
> +#define RG
;
> Changes in v2:
> - Reorder patches to get bindings first in the series.
> - Don't use child nodes in the device tree. Use #phy-cells=1 instead.
> - Update driver code with new 'xlate' function for the new device tree.
> - Minor changes in driver'
On Sat, 31 Oct 2020 13:22:43 +0100, Sergio Paracuellos wrote:
> Add bindings to describe Mediatek MT7621 PCIe PHY.
>
> Signed-off-by: Sergio Paracuellos
> ---
> .../bindings/phy/mediatek,mt7621-pci-phy.yaml | 36 +++
> 1 file changed, 36 insertions(+)
>
GENMASK(7, 6)
+#define RG_PE1_MSTCKDIV_VAL(x) ((0x3 & (x)) << 6)
+
+#define RG_PE1_FRC_MSTCKDIVBIT(5)
+
+#define XTAL_MODE_SEL_SHIFT6
+#define XTAL_MODE_SEL_MASK 0x7
+
+#define MAX_PHYS 2
+
+/**
+ * st
=1 instead.
- Update driver code with new 'xlate' function for the new device tree.
- Minor changes in driver's macros changing some spaces to tabs.
Thanks in advance for your time.
Best regards,
Sergio Paracuellos
Sergio Paracuellos (4):
dt-bindings: phy: Add binding
Add bindings to describe Mediatek MT7621 PCIe PHY.
Signed-off-by: Sergio Paracuellos
---
.../bindings/phy/mediatek,mt7621-pci-phy.yaml | 36 +++
1 file changed, 36 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml
diff --git a
_PE1_H_LCDDS_SSC_DELTA1_VAL(x) ((0xff & (x)) << 16)
> +
> +#define RG_PE1_LCDDS_CLK_PH_INV_REG0x4a0
> +#define RG_PE1_LCDDS_CLK_PH_INVBIT(5)
> +
> +#define RG_PE1_H_PLL_BR_REG0x4ac
> +#define RG_PE1_H_PLL_BR
ng some spaces to tabs.
Thanks in advance for your time.
Best regards,
Sergio Paracuellos
Sergio Paracuellos (2):
dt-bindings: phy: Add binding for Mediatek MT7621 PCIe PHY
phy: ralink: Add PHY driver for MT7621 PCIe PHY
.../bindings/phy/mediatek,mt7621-pci-phy.txt | 28 ++
drivers/phy
Add bindings to describe Mediatek MT7621 PCIe PHY.
Reviewed-by: Rob Herring
Signed-off-by: Sergio Paracuellos
---
.../bindings/phy/mediatek,mt7621-pci-phy.txt | 28 +++
1 file changed, 28 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/mediatek,mt7621
0x414
+#define RG_PE1_MSTCKDIVGENMASK(7, 6)
+#define RG_PE1_MSTCKDIV_VAL(x) ((0x3 & (x)) << 6)
+
+#define RG_PE1_FRC_MSTCKDIVBIT(5)
+
+#define MAX_PHYS 2
+
+/**
+ * struct mt7621_pci_phy_instance - Mt7621 Pci
GENMASK(11, 0)
> > +#define RG_PE1_H_LCDDS_SSC_DELTA_VAL(x) ((0xfff & (x)) << 0)
> > +#define RG_PE1_H_LCDDS_SSC_DELTA1GENMASK(27, 16)
> > +#define RG_PE1_H_LCDDS_SSC_DELTA1_VAL(x) ((0xff & (x)) << 16)
> > +
> >
)
> +#define RG_PE1_H_LCDDS_SSC_DELTA1_VAL(x) ((0xff & (x)) << 16)
> +
> +#define RG_PE1_LCDDS_CLK_PH_INV_REG 0x4a0
> +#define RG_PE1_LCDDS_CLK_PH_INV BIT(5)
> +
> +#define RG_PE1_H_PLL_BR_REG 0x4ac
> +#define RG_P
(x)) << 16)
> +
> +#define RG_PE1_LCDDS_CLK_PH_INV_REG0x4a0
> +#define RG_PE1_LCDDS_CLK_PH_INVBIT(5)
> +
> +#define RG_PE1_H_PLL_BR_REG0x4ac
> +#define RG_PE1_H_PLL_BRGENMASK(18, 16)
>
On Sat, 30 Mar 2019 06:50:37 +0100, Sergio Paracuellos wrote:
> Add bindings to describe Mediatek MT7621 PCIe PHY.
>
> Signed-off-by: Sergio Paracuellos
> ---
> .../bindings/phy/mediatek,mt7621-pci-phy.txt | 28 +++
> 1 file changed, 28 insertions(+)
>
n for the new device tree.
- Minor changes in driver's macros changing some spaces to tabs.
Thanks in advance for your time.
Best regards,
Sergio Paracuellos
Sergio Paracuellos (2):
dt-bindings: phy: Add binding for Mediatek MT7621 PCIe PHY
phy: ralink: Add PHY driver for MT7621 PCIe P
+#define RG_PE1_MSTCKDIVGENMASK(7, 6)
+#define RG_PE1_MSTCKDIV_VAL(x) ((0x3 & (x)) << 6)
+
+#define RG_PE1_FRC_MSTCKDIVBIT(5)
+
+#define MAX_PHYS 2
+
+/**
+ * struct mt7621_pci_phy_instance - Mt7621 Pci
Add bindings to describe Mediatek MT7621 PCIe PHY.
Signed-off-by: Sergio Paracuellos
---
.../bindings/phy/mediatek,mt7621-pci-phy.txt | 28 +++
1 file changed, 28 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.txt
diff --git a
Hi Rob,
Thanks for the review.
On Thu, Mar 28, 2019 at 4:42 PM Rob Herring wrote:
>
> On Thu, Mar 14, 2019 at 02:22:10PM +0100, Sergio Paracuellos wrote:
> > Add bindings to describe Mediatek MT7621 PCIe PHY.
>
> Binding should come before the driver.
Do you mean this should
On Thu, Mar 14, 2019 at 02:22:10PM +0100, Sergio Paracuellos wrote:
> Add bindings to describe Mediatek MT7621 PCIe PHY.
Binding should come before the driver.
>
> Signed-off-by: Sergio Paracuellos
> ---
> .../bindings/phy/mediatek,mt7621-pci-phy.txt | 54 ++
nt of this phy.
Both drivers have been tested together in a gnubee1 board.
Thanks in advance for your time.
Best regards,
Sergio Paracuellos
Sergio Paracuellos (2):
phy: ralink: Add PHY driver for MT7621 PCIe PHY
dt-bindings: phy: Add binding for Mediatek MT7621 PCIe PHY
.../bi
define RG_PE1_H_PLL_BR_REG0x4ac
+#define RG_PE1_H_PLL_BRGENMASK(18, 16)
+#define RG_PE1_H_PLL_BR_VAL(x) ((0x7 & (x)) << 16)
+
+#defineRG_PE1_MSTCKDIV_REG 0x414
+#define RG_PE1_MSTCKDIV GENMASK(7, 6)
Add bindings to describe Mediatek MT7621 PCIe PHY.
Signed-off-by: Sergio Paracuellos
---
.../bindings/phy/mediatek,mt7621-pci-phy.txt | 54 +++
1 file changed, 54 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.txt
diff --git a
0..33a8a698bdd0
--- /dev/null
+++ b/drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.txt
@@ -0,0 +1,54 @@
+Mediatek Mt7621 PCIe PHY
+
+Required properties:
+- compatible: must be "mediatek,mt7621-pci-phy"
+- reg: base address and length of the PCIe PHY block
+- #address-cells: mus
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