Attention:
First I would like to explain in detail, All issues relating to the project, I
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From: Dexuan Cui Sent: Thursday, July 18, 2019 8:23 PM
>
> The VP ASSIST PAGE is an "overlay" page (see Hyper-V TLFS's Section
> 5.2.1 "GPA Overlay Pages" for the details) and here is an excerpt:
>
> "
> The hypervisor defines several special p
The VP ASSIST PAGE is an "overlay" page (see Hyper-V TLFS's Section
5.2.1 "GPA Overlay Pages" for the details) and here is an excerpt:
"
The hypervisor defines several special pages that "overlay" the guest's
Guest Physical Addresses (GPA) space. Ov
> From: Thomas Gleixner
> Sent: Thursday, July 18, 2019 12:56 AM
> To: Dexuan Cui
>
> On Thu, 18 Jul 2019, Dexuan Cui wrote:
> >
> > The concept of the "overlay page" seems weird, and frankly speaking,
> > I don't really understand why the Hyper-V guys invented it, but as far
> > as this patch h
On Thu, 18 Jul 2019, Dexuan Cui wrote:
>
> The concept of the "overlay page" seems weird, and frankly speaking,
> I don't really understand why the Hyper-V guys invented it, but as far
> as this patch here is concerned, I think the patch is safe and it can
> indeed fix the CPU offlining issue I d
> From: Thomas Gleixner
> Sent: Thursday, July 18, 2019 12:01 AM
> ...
> Those are two different things. The GPF_ZERO allocation makes sense on its
> own but it _cannot_ prevent the following scenario:
Hi tglx,
The scenario can be prevented.
The VP ASSIST PAGE is an "overl
llocation is never freed.
> >
> > Neither the comment nor the changelog make any sense to me.
> > tglx
>
> That allocation was introduced by the commit
> a46d15cc1ae5 ("x86/hyper-v: allocate and use Virtual Processor Assist Pages").
>
> I think it's ok t
r hv_cpu_die() disables the
> > HV_X64_MSR_VP_ASSIST_PAGE, so hv_apic_eoi_write() may not write
> > the EOI MSR, if the apic_assist field's bit0 happens to be 1; as a result,
> > Hyper-V may not be able to deliver all the interrupts to the CPU, and the
> > CPU may not be stopped, and the kernel w
field's bit0 happens to be 1; as a result, Hyper-V
> may not be able to deliver all the interrupts to the CPU, and the CPU may
> not be stopped, and the kernel will hang soon.
>
> The VP ASSIST PAGE is an "overlay" page (see Hyper-V TLFS's Section
> 5.2.1 "
the apic_assist field's bit0 happens to be 1; as a result, Hyper-V
> may not be able to deliver all the interrupts to the CPU, and the CPU may
> not be stopped, and the kernel will hang soon.
>
> The VP ASSIST PAGE is an "overlay" page (see Hyper-V TLFS's Section
>
able to deliver all the interrupts to the CPU, and the CPU may
not be stopped, and the kernel will hang soon.
The VP ASSIST PAGE is an "overlay" page (see Hyper-V TLFS's Section
5.2.1 "GPA Overlay Pages"), so with this fix we're sure the apic_assist
field is stil
From: Ladi Prosek
Structure layout is specified in Hyper-V TLFS 5.0b.
The state related to the VP assist page is still managed by the LAPIC
code in the pv_eoi field.
Signed-off-by: Ladi Prosek
Signed-off-by: Vitaly Kuznetsov
---
arch/x86/include/uapi/asm/hyperv.h | 10 ++
arch/x86
Dear Sir/Madam,
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h
Dear Sir/Madam,
I am Sgt Swanson Dennis, I have a good business proposal for you.
There are no risks involved and it is easy. Please reply for briefs
and procedures.
Best regards,
Sgt Swanson Dennis
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h
Dear Sir/Madam,
I am Sgt Swanson Dennis, I have a good business proposal for you.
There are no risks involved and it is easy. Please reply for briefs
and procedures.
Best regards,
Sgt Swanson Dennis
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h
Dear Sir/Madam,
I am Sgt Anthony Victor, I have a good business proposal for you.
There are no risks involved and it is easy. Please reply for briefs
and procedures.
Best regards,
Sgt Anthony Victor
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Dear Sir/Madam,
I am Sgt Anthony Victor, I have a good business proposal for you.
There are no risks involved and it is easy. Please reply for briefs
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Best regards,
Sgt Anthony Victor
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