On Thu, Mar 06, 2014 at 05:04:25PM +0100, Denis Carikli wrote:
> According to the datasheet, setting the di0_polarity_disp_clk
> field in the GENERAL di register sets the output clock polarity
> to active high.
>
> Signed-off-by: Denis Carikli
> ---
> ChangeLog v8->v9:
> - New patch that is now n
According to the datasheet, setting the di0_polarity_disp_clk
field in the GENERAL di register sets the output clock polarity
to active high.
Signed-off-by: Denis Carikli
---
ChangeLog v8->v9:
- New patch that is now needed by the
"staging: imx-drm: Use de-active and pixelclk-active" patch.
---