[RESEND PATCH v5 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

This patchset ports CPU clock detection for MT7621 from OpenWrt and adds a complete clock plan for the mt7621 SOC. The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers

Re: [PATCH v5 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

Quoting Sergio Paracuellos (2021-01-17 06:19:36) > Hi all, > > On Sun, Dec 20, 2020 at 10:37 AM Sergio Paracuellos > wrote: > > > > - Hardcode "xtal" as parent in FIXED macro. > > - Change 'else if' clause into 'if' clause since a return statement was > >being used in 'mt7621_xtal_recalc_ra

Re: [PATCH v5 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

Hi all, On Sun, Dec 20, 2020 at 10:37 AM Sergio Paracuellos wrote: > > This patchset ports CPU clock detection for MT7621 from OpenWrt > and adds a complete clock plan for the mt7621 SOC. > > The documentation for this SOC only talks about two registers > regarding to the clocks: > * SYSC_REG_CPL

[PATCH v5 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

This patchset ports CPU clock detection for MT7621 from OpenWrt and adds a complete clock plan for the mt7621 SOC. The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers