> Phil Elwell hat am 17. September 2018 um 20:01
> geschrieben:
>
>
> On 17/09/2018 18:51, Florian Fainelli wrote:
> > On 09/17/2018 04:47 AM, Phil Elwell wrote:
> >> Hi Stefan,
> >>
> >> On 17/09/2018 12:39, Stefan Wahren wrote:
> >>> Hi Phil,
> >>>
> >>> Am 17.09.2018 um 10:22 schrieb Phil El
On 17/09/2018 18:51, Florian Fainelli wrote:
On 09/17/2018 04:47 AM, Phil Elwell wrote:
Hi Stefan,
On 17/09/2018 12:39, Stefan Wahren wrote:
Hi Phil,
Am 17.09.2018 um 10:22 schrieb Phil Elwell:
Both sides of the VCHIQ communications mechanism need to agree on the cache
line size. Using an in
On 09/17/2018 04:47 AM, Phil Elwell wrote:
> Hi Stefan,
>
> On 17/09/2018 12:39, Stefan Wahren wrote:
>> Hi Phil,
>>
>> Am 17.09.2018 um 10:22 schrieb Phil Elwell:
>>> Both sides of the VCHIQ communications mechanism need to agree on the cache
>>> line size. Using an incorrect value can lead to da
Hi Stefan,
On 17/09/2018 12:39, Stefan Wahren wrote:
> Hi Phil,
>
> Am 17.09.2018 um 10:22 schrieb Phil Elwell:
>> Both sides of the VCHIQ communications mechanism need to agree on the cache
>> line size. Using an incorrect value can lead to data corruption, but having
>> the
>> two sides using
Hi Phil,
Am 17.09.2018 um 10:22 schrieb Phil Elwell:
> Both sides of the VCHIQ communications mechanism need to agree on the cache
> line size. Using an incorrect value can lead to data corruption, but having
> the
> two sides using different values is usually worse.
>
> In the absence of an obvi
Both sides of the VCHIQ communications mechanism need to agree on the cache
line size. Using an incorrect value can lead to data corruption, but having the
two sides using different values is usually worse.
In the absence of an obvious convenient run-time method to determine the
correct value in t
