Re: [PATCH v11 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

2021-04-09 Thread Stephen Boyd
Quoting Sergio Paracuellos (2021-03-23 01:13:22) > On Tue, Mar 9, 2021 at 6:22 AM Sergio Paracuellos > wrote: > > > > Changes in v11: > > - Collect Rob's Reviewed-by in bindings documentation patch. > > - Fix MAINTAINERS patch using file 'mediatek,mt7621-sysc.yaml' > >for documentation bindi

Re: [PATCH v11 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

2021-03-23 Thread Sergio Paracuellos
Hi Stephen, On Tue, Mar 9, 2021 at 6:22 AM Sergio Paracuellos wrote: > > This patchset ports CPU clock detection for MT7621 from OpenWrt > and adds a complete clock plan for the mt7621 SOC. > > The documentation for this SOC only talks about two registers > regarding to the clocks: > * SYSC_REG_C

[PATCH v11 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

2021-03-08 Thread Sergio Paracuellos
This patchset ports CPU clock detection for MT7621 from OpenWrt and adds a complete clock plan for the mt7621 SOC. The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers