xdriverproject.org; o...@aepfle.de;
> a...@canonical.com; jasow...@redhat.com; t...@linutronix.de;
> h...@zytor.com
> Subject: Re: [PATCH 1/1] X86: hyperv: Enable MSR based APIC access
>
>
> * K. Y. Srinivasan wrote:
>
> > If the hypervisor supports MSR based access to the APIC
* K. Y. Srinivasan wrote:
> If the hypervisor supports MSR based access to the APIC registers
> (EOI, TPR and ICR), implement the MSR based access.
>
> Signed-off-by: K. Y. Srinivasan
> ---
> arch/x86/include/uapi/asm/hyperv.h |5 +++
> arch/x86/kernel/cpu/mshyperv.c | 69
> +++
If the hypervisor supports MSR based access to the APIC registers
(EOI, TPR and ICR), implement the MSR based access.
Signed-off-by: K. Y. Srinivasan
---
arch/x86/include/uapi/asm/hyperv.h |5 +++
arch/x86/kernel/cpu/mshyperv.c | 69
2 files changed
