[staging:staging-testing] BUILD SUCCESS 07ff20cf172f31f0dfbc456662f20339767c69fd

2021-04-13 Thread kernel test robot
allyesconfig powerpc allmodconfig powerpc allnoconfig x86_64 randconfig-a003-20210413 x86_64 randconfig-a002-20210413 x86_64 randconfig-a001-20210413 x86_64 randconfig-a005

Re: [PATCH v13 4/4] MAINTAINERS: add MT7621 CLOCK maintainer

2021-04-13 Thread Stephen Boyd
Quoting Sergio Paracuellos (2021-04-09 22:50:59) > Adding myself as maintainer for mt7621 clock driver. > > Signed-off-by: Sergio Paracuellos > --- Applied to clk-next ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproj

Re: [PATCH v13 3/4] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

2021-04-13 Thread Stephen Boyd
Quoting Sergio Paracuellos (2021-04-09 22:50:58) > Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml' > contains 'mediatek' as a valid vendor string. Some nodes in the device > tree are using an invalid vendor string vfor 'mtk' instead. Fix all of > them in dts file. Update als

Re: [PATCH v13 2/4] staging: mt7621-dts: make use of new 'mt7621-clk'

2021-04-13 Thread Stephen Boyd
Quoting Sergio Paracuellos (2021-04-09 22:50:57) > Clocks for SoC mt7621 have been properly integrated so there is > no need to declare fixed clocks at all in the device tree. Remove > all of them, add new device tree nodes for mt7621-clk and update > the rest of the nodes to use them. > > Acked-b

Re: [PATCH v13 1/4] clk: ralink: add clock driver for mt7621 SoC

2021-04-13 Thread Stephen Boyd
Quoting Sergio Paracuellos (2021-04-09 22:50:56) > The documentation for this SOC only talks about two > registers regarding to the clocks: > * SYSC_REG_CPLL_CLKCFG0 - provides some information about > boostrapped refclock. PLL and dividers used for CPU and some > sort of BUS. > * SYSC_REG_CPLL_CLK