22.11.2020 04:02, Ezequiel Garcia пишет:
> Hi Dmitry,
>
...
>> +++ b/drivers/staging/media/tegra-vde/TODO
>> @@ -0,0 +1,4 @@
>> +TODO:
>> + - Implement V4L2 API once it gains support for stateless decoders.
>> +
>> +Contact: Dmitry Osipenko
>
> The API for H264 stateless decoding is ready.
Hi Dmitry,
On Mon, 11 Dec 2017 at 21:27, Dmitry Osipenko wrote:
>
> NVIDIA Tegra20/30/114/124/132 SoC's have video decoder engine that
> supports standard set of video formats like H.264 / MPEG-4 / WMV / VC1.
>
> Signed-off-by: Dmitry Osipenko
> ---
> MAINTAINERS
On Sat, Nov 21, 2020 at 3:50 PM Sergio Paracuellos
wrote:
>
> Hi Rob,
>
> Thanks for the review.
>
> On Sat, Nov 21, 2020 at 2:34 PM Rob Herring wrote:
> >
> > On Fri, Nov 13, 2020 at 04:46:29PM +0100, Sergio Paracuellos wrote:
> > > Adds device tree binding documentation for clocks in the
> > >
Remove this driver from staging because it has been moved
into its properly place in the kernel.
Signed-off-by: Sergio Paracuellos
Acked-by: Greg Kroah-Hartman
---
drivers/staging/Kconfig | 2 -
drivers/staging/Makefile | 1 -
drivers/staging/mt762
Adding myself as maintainer for mt7621 pci phy driver.
Signed-off-by: Sergio Paracuellos
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f01ce8f451c8..c07967b9a654 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11108,6 +11108,12 @@ S:
This patch adds a driver for the PCIe PHY of MT7621 SoC.
Signed-off-by: Sergio Paracuellos
---
drivers/phy/ralink/Kconfig | 8 +
drivers/phy/ralink/Makefile | 1 +
drivers/phy/ralink/phy-mt7621-pci.c | 352
3 files changed, 361 insertions(+)
cre
This series adds support for the PCIe PHY found in the Mediatek
MT7621 SoC.
There is also a 'mt7621-pci' driver which is the controller part
which is still in staging and is a client of this phy.
Both drivers have been tested together in a gnubee1 board.
This series are rebased on the top of lin
Add bindings to describe Mediatek MT7621 PCIe PHY.
Signed-off-by: Sergio Paracuellos
Reviewed-by: Rob Herring
---
.../bindings/phy/mediatek,mt7621-pci-phy.yaml | 36 +++
1 file changed, 36 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/mediatek,mt7621-p
Hi Rob,
Thanks for the review.
On Sat, Nov 21, 2020 at 2:34 PM Rob Herring wrote:
>
> On Fri, Nov 13, 2020 at 04:46:29PM +0100, Sergio Paracuellos wrote:
> > Adds device tree binding documentation for clocks in the
> > MT7621 SOC.
> >
> > Signed-off-by: Sergio Paracuellos
> > ---
> > .../bindi
On Fri, Nov 13, 2020 at 04:46:29PM +0100, Sergio Paracuellos wrote:
> Adds device tree binding documentation for clocks in the
> MT7621 SOC.
>
> Signed-off-by: Sergio Paracuellos
> ---
> .../bindings/clock/mediatek,mt7621-clk.yaml | 61 +++
> 1 file changed, 61 insertions(+)
>
On Fri, 13 Nov 2020 16:46:28 +0100, Sergio Paracuellos wrote:
> Adds dt binding header for 'mediatek,mt7621-clk' clocks.
>
> Signed-off-by: Sergio Paracuellos
> ---
> include/dt-bindings/clock/mt7621-clk.h | 41 ++
> 1 file changed, 41 insertions(+)
> create mode 100644
From: Kaixu Xia
The bool variable is2T is true, so the if statement is redundant.
we can directly set the variable bound to 8 and remove the if
statement.
Reported-by: Tosk Robot
Signed-off-by: Kaixu Xia
---
drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c | 7 +--
1 file changed, 1 inserti
On 20-11-20, 17:20, Sergio Paracuellos wrote:
> Hi Vinod,
>
> On Thu, Nov 19, 2020 at 4:43 PM Sergio Paracuellos
> wrote:
> >
> > This series adds support for the PCIe PHY found in the Mediatek
> > MT7621 SoC.
> >
> > There is also a 'mt7621-pci' driver which is the controller part
> > which is s
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