From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5:
- Fix compiled error (Heiko
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes
2Gbps, 2.7Gbps, 5.4Gbps}.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rat
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v8:
- Modify the commit subject name. (Heiko)
Changes in v7: None
Changes in v6: None
Add dt binding documentation for rockchip display port PHY.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v8:
- Remove the specific address in the example node name. (Heiko)
Changes in v7:
- Simplify the commit message. (Kishon)
Changes in v6: None
Changes in v5
On 10/28/2015 05:23 AM, Heiko Stuebner wrote:
> Am Samstag, 24. Oktober 2015, 11:06:04 schrieb Yakir Yang:
>> Add phy driver for the Rockchip DisplayPort PHY module. This
>> is required to get DisplayPort working in Rockchip SoCs.
>>
>> Tested-by: Javier Martinez Canill
On 10/28/2015 05:23 AM, Heiko Stuebner wrote:
> Am Samstag, 24. Oktober 2015, 11:06:04 schrieb Yakir Yang:
>> Add phy driver for the Rockchip DisplayPort PHY module. This
>> is required to get DisplayPort working in Rockchip SoCs.
>>
>> Tested-by: Javier Martinez Canill
Hi Heiko,
On 10/28/2015 05:04 AM, Heiko Stuebner wrote:
> Hi Yakir,
>
> Am Samstag, 24. Oktober 2015, 11:06:00 schrieb Yakir Yang:
>> Analogix dp driver is split from exynos dp driver, so we just
>> make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
>>
&
24. Oktober 2015, 11:06:03 schrieb Yakir Yang:
>> Rockchip DP driver is a helper driver of analogix_dp coder driver,
>> so most of the DT property should be descriped in analogix_dp document.
>>
>> Tested-by: Javier Martinez Canillas
>> Signed-off-by: Yakir Yang
> everyt
On 10/28/2015 05:24 AM, Heiko Stuebner wrote:
> Am Samstag, 24. Oktober 2015, 11:06:37 schrieb Yakir Yang:
>> Add dt binding documentation for rockchip display port PHY.
>>
>> Tested-by: Javier Martinez Canillas
>> Signed-off-by: Yakir Yang
>> ---
> phy bindi
On 10/28/2015 07:08 AM, Heiko Stuebner wrote:
> Am Samstag, 24. Oktober 2015, 11:06:37 schrieb Yakir Yang:
>> Add dt binding documentation for rockchip display port PHY.
>>
>> Tested-by: Javier Martinez Canillas
>> Signed-off-by: Yakir Yang
>> ---
>> Cha
8 board. Also I have
tested on Samsung Snow and Peach Pit Chromebooks, and thanks to Javier at
Samsung
help to retest the whole series on Samsung Exynos5800 Peach Pi Chromebook,
glad to say that things works rightlly.
Thanks,
- Yakir
Changes in v8:
- Correct the right document path of display-ti
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
er is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
to avo
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6:
- Fix Peach Pit hpd property name
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v8:
- Fix the mixed spacers on macro definitions. (Heiko)
- Remove the unnecessary empty line after
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- Fix
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
C
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes
Hi Heiko,
On 10/29/2015 04:02 AM, Heiko Stuebner wrote:
> Hi Yakir,
>
> Am Mittwoch, 28. Oktober 2015, 16:26:33 schrieb Yakir Yang:
>> diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
>> b/Documentation/devicetree/bindings/display/exynos/exynos_dp
Hi Heiko,
On 10/29/2015 04:36 AM, Heiko Stuebner wrote:
> Hi Yakir,
>
> Am Mittwoch, 28. Oktober 2015, 16:30:33 schrieb Yakir Yang:
>> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
>> +{
>> +struct device *dev = &pdev->dev;
>> +
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v9:
- Removed the unused the variable "res" in probe function. (Heiko)
- Removed the unused
On 10/29/2015 04:40 PM, Heiko Stuebner wrote:
> Am Donnerstag, 29. Oktober 2015, 09:12:21 schrieb Yakir Yang:
>> Hi Heiko,
>>
>> On 10/29/2015 04:02 AM, Heiko Stuebner wrote:
>>> Hi Yakir,
>>>
>>> Am Mittwoch, 28. Oktober 2015, 16:26:33 schrieb Y
Hi Heiko,
On 10/30/2015 01:49 AM, Heiko Stuebner wrote:
> Am Mittwoch, 28. Oktober 2015, 16:15:43 schrieb Yakir Yang:
>> Hi all,
>>
>> The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>> share the same IP, so a lot of parts can be re-used. I sp
anillas
Signed-off-by: Yakir Yang
---
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Add "analogix,need-force-hpd" to indicate whether driver need foce
hpd when hpd detect failed.
Changes in v2: No
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
Signed-off-by: Yakir Yang
Reviewed-by: Heiko Stuebner
---
Changes in v9:
- Document more details for 'ports' property
On 10/31/2015 02:30 PM, Yakir Yang wrote:
> Rockchip DP driver is a helper driver of analogix_dp coder driver,
> so most of the DT property should be descriped in analogix_dp document.
>
> Signed-off-by: Yakir Yang
>
> Signed-off-by: Yakir Yang
> Reviewed-by: Heiko Stueb
On 10/31/2015 12:42 AM, Rob Herring wrote:
> On Wed, Oct 28, 2015 at 3:31 AM, Yakir Yang wrote:
>> Add dt binding documentation for rockchip display port PHY.
>>
>> Reviewed-by: Heiko Stuebner
>> Signed-off-by: Yakir Yang
> Acked-by: Rob Herring
Thanks,
-
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v10:
- Removed the duplicated signed-of.
Changes in v9:
- Document more details for
Hi Rob,
On 10/31/2015 12:46 AM, Rob Herring wrote:
> On Wed, Oct 28, 2015 at 3:28 AM, Yakir Yang wrote:
>> Rockchip DP driver is a helper driver of analogix_dp coder driver,
>> so most of the DT property should be descriped in analogix_dp document.
>>
>> Reviewed-by
Hi Heiko,
å¨ 09/02/2015 05:00 AM, Heiko Stuebner åé:
> Hi Yakir,
>
> Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
>> Rockchip have three clocks for dp controller, we leave pclk_edp
>> to analogix_dp driver control, and keep the sclk_edp_24m and
>>
Hi Heiko,
å¨ 2015/9/1 22:24, Heiko Stuebner åé:
> Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
>> Rockchip have three clocks for dp controller, we leave pclk_edp
>> to analogix_dp driver control, and keep the sclk_edp_24m and
>> sclk_edp in platform dri
Hi Heiko,
å¨ 09/02/2015 12:51 AM, Heiko Stuebner åé:
> Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
>> This phy driver would control the Rockchip DisplayPort module
>> phy clock and phy power, it is relate to analogix_dp-rockchip
>> dp driver. If you wan
Heiko,
å¨ 09/02/2015 04:46 AM, Heiko Stuebner åé:
> Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
>> Split the dp core driver from exynos directory to bridge
>> directory, and rename the core driver to analogix_dp_*,
>> leave the platform code
Hi Heiko,
å¨ 09/02/2015 04:58 AM, Heiko Stuebner åé:
> Hi Yakir,
>
> small nit more below
>
> Am Dienstag, 1. September 2015, 18:51:16 schrieb Heiko Stuebner:
>> Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
>>> +- clocks: from common clo
Hi Heiko,
å¨ 09/02/2015 05:47 AM, Heiko Stuebner åé:
> Hi Yakir,
>
> Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
>> The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>> share the same IP, so a lot of parts can be re-used. I spl
Thierry,
å¨ 2015/9/2 16:34, Thierry Reding åé:
> On Wed, Sep 02, 2015 at 10:06:36AM +0800, Yakir Yang wrote:
>> å¨ 09/02/2015 05:00 AM, Heiko Stuebner åé:
>>> Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
> [...]
>>>> diff
Hi Heiko,
å¨ 09/02/2015 05:00 AM, Heiko Stuebner åé:
> Hi Yakir,
>
> Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
>> From: Mark Yao
>>
>> Add bpc and color mode setting in rockchip_drm_vop driver, so
>> connector could try to use the edid
Hi Rob,
å¨ 09/02/2015 09:27 PM, Rob Herring åé:
> On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang wrote:
>> This phy driver would control the Rockchip DisplayPort module
>> phy clock and phy power, it is relate to analogix_dp-rockchip
>> dp driver. If you want DP work
Hi Emil,
å¨ 09/02/2015 10:50 PM, Emil Velikov åé:
> [Dropping the CC list]
Hmm...Don't understand what this means. If you can explain, that
would be better, so I would not miss your suggest. :-)
> Hi Yakir Yang,
>
> On 1 September 2015 at 06:49, Yakir Yang wrote:
>
Hi Rob,
å¨ 09/03/2015 04:17 AM, Rob Herring åé:
> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang wrote:
>> Some edp screen do not have hpd signal, so we can't just return
>> failed when hpd plug in detect failed.
> This is a property of the panel (or connector perha
Hi Krzysztof,
å¨ 09/03/2015 08:01 AM, Krzysztof Kozlowski åé:
> On 01.09.2015 15:01, Yakir Yang wrote:
>> After exynos_dp have been splited the common IP code into analogix_dp driver,
> s/splited/split/
Done :)
>> the analogix_dp driver have deprecated some samsung p
Hi Krzysztof,
å¨ 09/03/2015 01:08 PM, Krzysztof Kozlowski åé:
> On 03.09.2015 14:04, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> å¨ 09/03/2015 08:21 AM, Krzysztof Kozlowski åé:
>>> On 01.09.2015 14:46, Yakir Yang wrote:
>>>> After run "chec
Hi Krzysztof,
å¨ 09/03/2015 08:21 AM, Krzysztof Kozlowski åé:
> On 01.09.2015 14:46, Yakir Yang wrote:
>> After run "checkpatch.pl -f --subjective" command, I see there
>> are lots of alignment problem in exynos_dp driver, so let just
>> fix them.
> Hi,
>
Hi Joe,
å¨ 09/03/2015 01:57 PM, Joe Perches åé:
> On Thu, 2015-09-03 at 13:33 +0800, Yakir Yang wrote:
> []
>>>>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
> []
>>>>>> @@ -155,24 +156,22 @@ static int exynos_dp
Hi Krzysztof,
å¨ 09/03/2015 04:04 PM, Krzysztof Kozlowski åé:
> On 01.09.2015 14:55, Yakir Yang wrote:
>> Both hsync/vsync polarity and interlace mode can be parsed from
>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>> by the video code, same to
Hi Thierry,
å¨ 09/03/2015 04:38 PM, Thierry Reding åé:
> On Wed, Sep 02, 2015 at 06:02:25PM +0800, Yakir Yang wrote:
>> å¨ 2015/9/2 16:34, Thierry Reding åé:
> [...]
>>> At the very least your code must compile when applied against a recent
>>> upstream tr
Hi Thierry,
å¨ 09/03/2015 05:04 PM, Thierry Reding åé:
> On Thu, Sep 03, 2015 at 12:27:47PM +0800, Yakir Yang wrote:
>> Hi Rob,
>>
>> å¨ 09/03/2015 04:17 AM, Rob Herring åé:
>>> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang wrote:
>>>> Some edp
Hi Krzysztof,
å¨ 09/04/2015 08:36 AM, Krzysztof Kozlowski åé:
> On 01.09.2015 15:07, Yakir Yang wrote:
>
> Empty commit message. Please explain here why you want to add platform
> device type support.
>
> Actually the title is confusing. You are not adding support for platf
Hi Krzysztof,
å¨ 09/04/2015 08:41 AM, Krzysztof Kozlowski åé:
> On 03.09.2015 14:30, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> å¨ 09/03/2015 08:58 AM, Krzysztof Kozlowski åé:
>>> On 01.09.2015 14:49, Yakir Yang wrote:
>>>> Split the dp c
Hi Rob,
å¨ 09/05/2015 05:46 AM, Rob Herring åé:
> On Wed, Sep 2, 2015 at 11:27 PM, Yakir Yang wrote:
>> Hi Rob,
>>
>> å¨ 09/03/2015 04:17 AM, Rob Herring åé:
>>> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang wrote:
>>>> Some edp screen do no
Hi Krzysztof,
å¨ 09/03/2015 08:58 AM, Krzysztof Kozlowski åé:
> On 01.09.2015 14:49, Yakir Yang wrote:
>> Split the dp core driver from exynos directory to bridge
>> directory, and rename the core driver to analogix_dp_*,
>> leave the platform code to analogix_dp-exynos
Hi Heiko,
å¨ 09/03/2015 09:52 PM, Heiko Stuebner åé:
> Am Donnerstag, 3. September 2015, 11:25:00 schrieb Yakir Yang:
>> å¨ 09/02/2015 09:27 PM, Rob Herring åé:
>>> On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang wrote:
>>>> +- clocks: from common clo
Hi Krzysztof,
å¨ 09/07/2015 08:22 AM, Krzysztof Kozlowski åé:
> On 06.09.2015 16:49, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> å¨ 09/04/2015 08:41 AM, Krzysztof Kozlowski åé:
>>> On 03.09.2015 14:30, Yakir Yang wrote:
>>>> Hi Krzysztof,
&g
Hi Krzysztof,
å¨ 09/07/2015 07:55 AM, Krzysztof Kozlowski åé:
> On 06.09.2015 13:07, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> å¨ 09/04/2015 08:36 AM, Krzysztof Kozlowski åé:
>>> On 01.09.2015 15:07, Yakir Yang wrote:
>>>
>>> Empty commit
Hi Heiko,
On 09/02/2015 10:15 AM, Yakir Yang wrote:
> Hi Heiko,
>
> å¨ 09/02/2015 05:47 AM, Heiko Stuebner åé:
>> Hi Yakir,
>>
>> Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
>>> The Samsung Exynos eDP controller and Rockchip RK3288 eD
Hi Thierry & Rob,
Sorry, apologize for the delay in replying :-)
On 09/07/2015 04:20 PM, Thierry Reding wrote:
> On Sun, Sep 06, 2015 at 11:59:08AM +0800, Yakir Yang wrote:
>> Hi Thierry,
>>
>> å¨ 09/03/2015 05:04 PM, Thierry Reding åé:
>>> On Thu, Sep 0
Hi Heiko,
On 12/15/2015 08:06 AM, Heiko Stübner wrote:
> Hi Yakir,
>
> Am Montag, 7. Dezember 2015, 14:37:19 schrieb Yakir Yang:
>> The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>> share the same IP, so a lot of parts can be re-used. I split th
8 board. Also I have
tested on Samsung Snow and Peach Pit Chromebooks, and thanks to Javier at
Samsung
help to retest the whole series on Samsung Exynos5800 Peach Pi Chromebook,
glad to say that things works rightlly.
Thanks,
- Yakir
Changes in v11:
- Uses tabs to fix the indent
t the connector.
They reason why connector need register in helper driver is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.
Signed-o
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Signed-off-by: Yakir Yang
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
---
Changes in v11: None
Changes in v10: None
Changes in v9: None
2Gbps, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- A
: Yakir Yang
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
---
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-high&qu
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
Acked-by: Rob Herring
Tested-by
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Signed-off-by: Yakir Yang
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
---
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v11: None
Changes in v10:
- Correct the ROCKCHIP_ANALOGIX_DP
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
Acked-by: Rob Herring
Reviewed-by: Heiko Stuebner
---
Changes in v11: None
Changes in v10:
- Add the ack from Rob Herring
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Signed-off-by: Yakir Yang
Reviewed-by: Heiko Stuebner
---
Changes in v11: None
Changes in v10:
- Fix the wrong macro value of GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK
BIT(4
Add dt binding documentation for rockchip display port PHY.
Signed-off-by: Yakir Yang
Acked-by: Rob Herring
Reviewed-by: Heiko Stuebner
---
Changes in v11:
- Correct the title of this rockchip dp phy document(Rob)
- Add the ack from Rob Herring
Changes in v10: None
Changes in v9: None
Changes
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v11: None
Changes in v10:
- Remove the surplus "plat_data" che
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
Acked-by: Rob Herring
Te
do not start enabling DP at bind() phase
But for now the connector status don't hardcode to connected,
need to operate dp phy in .detect function, so we need to revert
parts if Gustavo Padovan's changes, add phy poweron
function in bind time.
Signed-off-by: Yakir Yang
Tested-by: Javier M
:
drm/exynos: do not start enabling DP at bind() phase
But for now driver need to read edid message in .get_modes()
function, so controller must be inited in bind time, so we
need to add controller init back.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v11: None
;t have this problem, then driver would received
the reply command very soon, so no more additional wait time would bring
to Exynos platform.
Signed-off-by: Yakir Yang
---
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Turn off the panel power in suspend time would help to reduce
power waste.
Signed-off-by: Yakir Yang
---
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes
sh before
encoder disabled.
The flush work in bridge disable time is try to ensure the HPD event
won't be missed before display card disabled, actually we can take a
fast respond way(interrupt thread) to update DRM HPD event to fix the
delay update and possible dead lock.
Signed-off-by: Yakir Y
Hi Heiko,
On 12/18/2015 07:51 AM, Heiko Stübner wrote:
> Hi Yakir,
>
> Am Mittwoch, 16. Dezember 2015, 11:20:18 schrieb Yakir Yang:
>> The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>> share the same IP, so a lot of parts can be re-used. I split th
Hi Mark
On 12/21/2015 03:25 PM, Mark yao wrote:
> Hi Yakir
> I want to convert drm/rockchip to support atomic api,
> I'd like you can do some modify to adapt it.
>
Sure, would update as soon as possible.
Thanks,
- Yakir
> - Mark
>
> On 2015å¹´11æ11æ¥ 15:4
Hi Mark,
On 12/21/2015 03:31 PM, Mark yao wrote:
> On 2015å¹´11æ11æ¥ 15:46, Yakir Yang wrote:
>> +hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
>> +
>> +drm_connector_helper_add(&hdmi->connector,
>> + &inno_hdmi_connector_help
Hi Jingoo,
Thanks for your respond.
On 12/22/2015 08:20 PM, Jingoo Han wrote:
> On Wednesday, December 16, 2015 12:41 PM, Yakir Yang wrote:
>> Add phy driver for the Rockchip DisplayPort PHY module. This
>> is required to get DisplayPort working in Rockchip SoCs.
>>
>>
On 12/22/2015 08:13 PM, Jingoo Han wrote:
> On Wednesday, December 16, 2015 12:35 PM, Yakir Yang wrote:
>> After exynos_dp have been split the common IP code into analogix_dp driver,
>> the analogix_dp driver have deprecated some Samsung platform properties which
>> could
Hi Jingoo,
Thanks for your respond.
On 12/22/2015 08:09 PM, Jingoo Han wrote:
> On Wednesday, December 16, 2015 12:28 PM, Yakir Yang wrote:
>> link_rate and lane_count already configured in analogix_dp_set_link_train(),
>> so we don't need to config those repeatly after tra
On 12/22/2015 08:05 PM, Jingoo Han wrote:
> On Wednesday, December 16, 2015 12:26 PM, Yakir Yang wrote:
>> Fix some obvious alignment problems, like alignment and line
>> over 80 characters problems, make this easy to be maintained
>> later.
>>
>> Signed-o
Hi Jingoo,
On 12/22/2015 08:26 PM, Jingoo Han wrote:
> On Wednesday, December 16, 2015 12:58 PM, Yakir Yang wrote:
>> After test on rockchiop platform, i found sometims driver would failed
>> at reading EDID message. After debugging more, i found that it's okay
>> to re
Hi Jingoo,
On 12/23/2015 12:24 PM, Yakir Yang wrote:
> Hi Jingoo,
>
> On 12/22/2015 08:26 PM, Jingoo Han wrote:
>> On Wednesday, December 16, 2015 12:58 PM, Yakir Yang wrote:
>>> After test on rockchiop platform, i found sometims driver would failed
>>> at read
ed on Rockchip Pinky Chromebook, haven't tested
on Samsung platform yet(would test later).
Thanks,
- Yakir
Changes in v12:
- Move the connector init to analogix_dp driver, and using ATOMIC helper(Heiko)
- Add the ack from Jingoo
- Remove the enum link_rate_type struct, using the marcos in drm_d
t the connector.
They reason why connector need register in helper driver is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.
Signe
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Signed-off-by: Yakir Yang
Acked-by: Jingoo Han
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
---
Changes in v12:
- Add the ack from Jingoo
2Gbps, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v12:
- Remove the enum link_rate_type struct, using the marcos in drm_dp_helper.h
(Jingoo)
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Ch
: Yakir Yang
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
---
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
Acked-by: Rob Herring
---
Changes in
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Signed-off-by: Yakir Yang
Reviewed-by: Krzysztof Kozlowski
Reviewed-by: Jingoo Han < jingoohan1 at gmail.com>
Tested-by: Javier Martinez Canillas
---
Changes in v12: None
Changes
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