From: Jérôme Glisse
When GPU fails to resume we can not trust that value we write to GPU
memory will post and we might get garbage (more like 0x on
x86) when reading them back. This trigger out of range memory access
in the kernel inside the vce resume code path.
This patch use canonical
From: Jerome Glisse
This fix black screen on resume issue that some people are
experiencing. There is a bug in the atombios code regarding
pll/crtc mapping. The atombios code reverse the logic for
the pll and crtc mapping.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/atombios_crtc.c
From: Jerome Glisse
This fix black screen on resume issue that some people are
experiencing. There is a bug in the atombios code regarding
pll/crtc mapping. The atombios code reverse the logic for
the pll and crtc mapping.
v2: DCE3 or DCE2 only have 2 crtc
Signed-off-by: Jerome Glisse
---
dri
From: Jerome Glisse
There is a rare case, that seems to only happen accross suspend/resume
cycle, where a bo is associated with several different handle. This
lead to a deadlock in ttm buffer reservation path. This could only
happen with flinked(globaly exported) object. Userspace should not
reop
From: Jerome Glisse
To avoid kernel rejecting cs if we return different global name
for same bo keep track of global name and always return the same.
Seems to fix issue with suspend/resume failing and repeatly printing
following message :
[drm:radeon_cs_ioctl] *ERROR* Failed to parse relocation -
From: Jerome Glisse
It make no sense to preserve caching state especialy when
moving from vram to system. It burden the page allocator to
match the vram caching (often WC) which just burn CPU cycle
for no good reasons.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/ttm/ttm_bo.c | 15 +++-
So i spend the day looking at ttm and eviction. The first patch i sent
earlier is i believe something that should be merged. This patch however
is more about discussing if other people are interested in similar mecanism
to be share among driver through ttm. I could otherwise just move its logic
to
From: Jerome Glisse
This patch add a minimum residency time configurable for each memory
pool (VRAM, GTT, ...). Intention is to avoid having a lot of memory
eviction from VRAM up to a point where the GPU pretty much spend all
it's time moving things in and out.
Signed-off-by: Jerome Glisse
---
From: Jerome Glisse
Force the use of cached memory when evicting from vram on non agp
hardware. Also force write combine on agp hw. This is to insure
the minimum cache type change when allocating memory and improving
memory eviction especialy on pci/pcie hw.
Signed-off-by: Jerome Glisse
---
dr
From: Jerome Glisse
If GPU reset fails the gart table ptr might be NULL avoid a
kernel segfault in this rare event.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/r600.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/
So as a followup is 2 patch. The first one just stop trying to move
object at each cs ioctl i believe it could be included in 3.7 as it
improve performances (especialy with vram change from userspace).
The second one implement a vram eviction policy. It's a simple one,
buffer used for write operat
From: Jerome Glisse
The bo creation placement is where the bo will be. Instead of trying
to move bo at each command stream let this work to another worker
thread that will use more advance heuristic.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/radeon.h| 1 +
drivers/gpu/dr
From: Jerome Glisse
Use delayed work thread to move buffer out of vram if they haven't
been use over some period of time. This allow to make room for
buffer that are actively use.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/radeon.h| 13 ++
drivers/gpu/drm/radeon/radeon_cs
From: Jerome Glisse
Set the proper number of tile pipe that should be a multiple of
pipe depending on the number of se engine.
Fix:
https://bugs.freedesktop.org/show_bug.cgi?id=56405
https://bugs.freedesktop.org/show_bug.cgi?id=56720
v2: Don't change sumo2
Signed-off-by: Jerome Glisse
Cc: sta
From: Jerome Glisse
The dma ring can't write to register thus have to write to memory
its fence value. This ensure that it doesn't try to use scratch
register for dma ring fence driver.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/r600.c | 3 ++-
drivers/gpu/drm/radeon/radeo
From: Jerome Glisse
Fix the size computation of the htile buffer.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/evergreen_cs.c | 17 +--
drivers/gpu/drm/radeon/r600_cs.c | 92 ---
drivers/gpu/drm/radeon/radeon_drv.c | 3 +-
3 files changed,
From: Jerome Glisse
After lockup we need to resume fence to last sync sequence and not
last received sequence so that all thread waiting on command stream
that lockedup resume. Otherwise GPU reset will be ineffective in most
cases.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/radeon
From: Jerome Glisse
Modeset path seems to conflict sometimes with the memory management
leading to kernel deadlock. This move modesetting reset after GPU
acceleration reset.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/radeon_device.c | 3 ++-
1 file changed, 2 insertions(+), 1 dele
From: Jerome Glisse
Force all fence to signal if GPU reset failed so no process get stuck
on waiting fence.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/radeon.h| 1 +
drivers/gpu/drm/radeon/radeon_device.c | 1 +
drivers/gpu/drm/radeon/radeon_fence.c | 19 +++
From: Jerome Glisse
radeon_fence_wait_empty_locked should not trigger GPU reset as no
place where it's call from would benefit from such thing and it
actually lead to a kernel deadlock in case the reset is triggered
from pm codepath. Instead force ring completion in place where it
makes sense or
From: Jerome Glisse
To make it easier to debug some lockup from userspace add support
to MEM_WRITE packet.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/evergreen_cs.c | 29 +
drivers/gpu/drm/radeon/r600_cs.c | 29 +
driver
From: Jerome Glisse
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/radeon_ring.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c
b/drivers/gpu/drm/radeon/radeon_ring.c
index ebd6956..9410e43 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
From: Jerome Glisse
To help debug dma related lockup.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/evergreen.c | 4
drivers/gpu/drm/radeon/evergreend.h | 3 +++
drivers/gpu/drm/radeon/ni.c | 4
drivers/gpu/drm/radeon/nid.h| 1 -
drivers/gpu/drm/radeon/r600
From: Jerome Glisse
Print 32dword before last know rptr as problem most likely comes
from previous command. Also small cosmetic change to the printing.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/radeon_ring.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions
From: Jerome Glisse
This try to reset the dma engine when performing gpu reset. Hopefully
bringing back the gpu dma engine in sane state.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/evergreen.c | 30 +-
drivers/gpu/drm/radeon/evergreend.h | 10 +
From: Jerome Glisse
Those rn50 chip are often connected to console remoting hw and load
detection often fails with those. Just don't try to load detect and
report connect.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/radeon_legacy_encoders.c | 8
1 file changed, 8 insertion
From: Jerome Glisse
We were checking the index against the size of the relocation buffer
instead of against the last index. This fix kernel segfault when
userspace submit ill formated command stream/relocation buffer pair.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/r600_cs.c | 6 +
From: Jerome Glisse
This simplify and cleanup the async dma checking.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/evergreen.c| 16 +-
drivers/gpu/drm/radeon/evergreen_cs.c | 807 +-
drivers/gpu/drm/radeon/evergreend.h | 29 +-
3 files changed
From: Jerome Glisse
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/radeon.h | 2 ++
drivers/gpu/drm/radeon/radeon_ring.c | 2 ++
drivers/gpu/drm/radeon/radeon_semaphore.c | 4
3 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/g
From: Jerome Glisse
Aruba and newer gpu does not need the avivo cursor work around,
quite the opposite this work around lead to corruption.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/radeon_cursor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/dr
From: Jerome Glisse
If spread spectrum is enabled and in use for a given pll we
should not turn it off as it will lead to turning off display
for crtc that use the pll (this behavior was observed on chelsea
edp).
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/radeon/atombios_crtc.c | 25 ++
From: Jerome Glisse
It seems some of those IGP dislike non dma32 page.
https://bugzilla.redhat.com/show_bug.cgi?id=785375
Signed-off-by: Jerome Glisse
Cc:
---
drivers/gpu/drm/radeon/radeon_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/rad
From: Jerome Glisse
It seems some of those IGP dislike non dma32 page despite what
documentation says. Fix regression since we allowed non dma32
pages. It seems it only affect some revision of those IGP chips
as we don't know which one just force dma32 for all of them.
https://bugzilla.redhat.co
From: Jerome Glisse
In case of multiple page table for GART, driver want to know which
buffer object is being bind/unbind. This allow driver to bind/unbind
buffer object from several different GART.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/nouveau/nouveau_bo.c |3 ++-
drivers/gpu
From: Jerome Glisse
After GPU lockup VRAM gart table is unpinned and thus its pointer
becomes unvalid. This patch move the unpin code to a common helper
function and set pointer to NULL so that page update code can check
if it should update GPU page table or not. That way bo still bound
to GART c
From: Jerome Glisse
Since force handling rework of d0d0a225e6ad43314c9aa7ea081f76adc5098ad4
we could end up bouncing connector status btw disconnected and unknown.
When connector status change a call to output_poll_changed happen which
in turn ask again for detect but with force set.
So set the
From: Jerome Glisse
Cayman seems to be particularly sensitive to read cache returning
old data after bind/unbind to GTT. Flush read cache for GTT range
with each fences for all new hw. Should fix several rendering glitches.
Like
V2 flush whole address space
https://bugs.freedesktop.org/show_bug
From: Jerome Glisse
Cayman seems to be particularly sensitive to read cache returning
old data after bind/unbind to GTT. Flush read cache for GTT range
with each fences for all new hw. Should fix several rendering glitches.
Like
V2 flush whole address space
V3 also flush shader read cache
https
From: Jerome Glisse
Polarity needs to be set accordingly to connector status (connected
or disconnected). Set it up at module init so first hotplug works
reliably no matter what is the initial set of connector.
Signed-off-by: Jerome Glisse
cc: sta...@kernel.org
---
drivers/gpu/drm/radeon/radeo
Hi,
So attached is last batch of patch, i split the ttm put page
fix and i fixed a bug in the pages alloc when clear flags
wasn't set. I tested them on a bunch of radeon and everythings
seems fine (several gl app, firefox, compositor ...). I will
do more testing on agp and nouveau tomorrow.
The l
From: Jerome Glisse
This was never use in none of the driver, properly using userspace
page for bo would need more code (vma interaction mostly). Removing
this dead code in preparation of ttm_tt & backend merge.
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
---
drivers/gpu/d
From: Jerome Glisse
Split btw highmem and lowmem page was rendered useless by the
pool code. Remove it. Note further cleanup would change the
ttm page allocation helper to actualy take an array instead
of relying on list this could drasticly reduce the number of
function call in the common case o
From: Jerome Glisse
This field is not use by any of the driver just drop it.
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
---
drivers/gpu/drm/radeon/radeon_ttm.c |1 -
include/drm/ttm/ttm_bo_driver.h |2 --
2 files changed, 0 insertions(+), 3 deletions(-)
diff
From: Jerome Glisse
On failure we need to make sure the page we free has wb cache
attribute. Do this pas call the proper ttm page helper function.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/ttm/ttm_tt.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/
From: Jerome Glisse
Use the ttm_tt page ptr array for page allocation, move the list to
array unwinding into the page allocation functions.
V2 split the fix to use ttm put page as a separate fix
properly fill pages array when TTM_PAGE_FLAG_ZERO_ALLOC is not
set
Signed-off-by: Jerome Glisse
---
From: Jerome Glisse
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/ttm/ttm_tt.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 2dd45ca..58ea7dc 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/
From: Jerome Glisse
ttm_backend will exist only and only with a ttm_tt, and ttm_tt
will be of interesting use only when bind to a backend. Thus to
avoid code & data duplication btw the two merge them.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/nouveau/nouveau_bo.c| 14 ++-
drivers/
From: Jerome Glisse
Move the page allocation and freeing to driver callback and
provide ttm code helper function for those.
Most intrusive change, is the fact that we now only fully
populate an object this simplify some of code designed around
the page fault design.
Signed-off-by: Jerome Glisse
From: Jerome Glisse
After GPU lockup VRAM gart table is unpinned and thus its pointer
becomes unvalid. This patch move the unpin code to a common helper
function and set pointer to NULL so that page update code can check
if it should update GPU page table or not. That way bo still bound
to GART c
Hi,
So updated patchset, only patch 5 seen change since last set.
Last 3 patch are from your patchset, modified on top of mine.
Konrad so i added you dma pool allocator on top of that
and added support for it to radeon. All in all it's slightly
smaller than your patchset.
Biggest change is use o
From: Jerome Glisse
This was never use in none of the driver, properly using userspace
page for bo would need more code (vma interaction mostly). Removing
this dead code in preparation of ttm_tt & backend merge.
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
---
drivers/gpu/d
From: Jerome Glisse
Split btw highmem and lowmem page was rendered useless by the
pool code. Remove it. Note further cleanup would change the
ttm page allocation helper to actualy take an array instead
of relying on list this could drasticly reduce the number of
function call in the common case o
From: Jerome Glisse
This field is not use by any of the driver just drop it.
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
---
drivers/gpu/drm/radeon/radeon_ttm.c |1 -
include/drm/ttm/ttm_bo_driver.h |2 --
2 files changed, 0 insertions(+), 3 deletions(-)
diff
From: Jerome Glisse
On failure we need to make sure the page we free has wb cache
attribute. Do this pas call the proper ttm page helper function.
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
---
drivers/gpu/drm/ttm/ttm_tt.c |5 -
1 files changed, 4 insertions(+), 1
From: Jerome Glisse
Use the ttm_tt page ptr array for page allocation, move the list to
array unwinding into the page allocation functions.
V2 split the fix to use ttm put page as a separate fix
properly fill pages array when TTM_PAGE_FLAG_ZERO_ALLOC is not
set
V3 Added back page_count()==1 chec
From: Jerome Glisse
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
---
drivers/gpu/drm/ttm/ttm_tt.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 2dd45ca..58ea7dc 100644
--- a/drivers
From: Jerome Glisse
ttm_backend will exist only and only with a ttm_tt, and ttm_tt
will be of interesting use only when bind to a backend. Thus to
avoid code & data duplication btw the two merge them.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/nouveau/nouveau_bo.c| 14 ++-
drivers/
From: Jerome Glisse
Move the page allocation and freeing to driver callback and
provide ttm code helper function for those.
Most intrusive change, is the fact that we now only fully
populate an object this simplify some of code designed around
the page fault design.
Signed-off-by: Jerome Glisse
From: Konrad Rzeszutek Wilk
In TTM world the pages for the graphic drivers are kept in three different
pools: write combined, uncached, and cached (write-back). When the pages
are used by the graphic driver the graphic adapter via its built in MMU
(or AGP) programs these pages in. The programming
From: Konrad Rzeszutek Wilk
As a mechanism to detect whether SWIOTLB is enabled or not.
We also fix the spelling - it was swioltb instead of
swiotlb.
CC: FUJITA Tomonori
[v1: Ripped out swiotlb_enabled]
Signed-off-by: Konrad Rzeszutek Wilk
---
drivers/xen/swiotlb-xen.c |2 +-
include/linu
From: Konrad Rzeszutek Wilk
With the exception that we do not handle the AGP case. We only
deal with PCIe cards such as ATI ES1000 or HD3200 that have been
detected to only do DMA up to 32-bits.
CC: Dave Airlie
CC: Alex Deucher
Signed-off-by: Konrad Rzeszutek Wilk
Reviewed-by: Jerome Glisse
Ok so here is full patchset, including nouveau support, Ben if you
could review (if change to nouveau in patch 7 are correct then others
change to nouveau are more than likely 100% correct :)).
So been tested on R7XX,EVERGREEN,CAICOS,CAYMAN with SWIOTLB. Also
tested on NV50. I still need to test A
From: Jerome Glisse
This was never use in none of the driver, properly using userspace
page for bo would need more code (vma interaction mostly). Removing
this dead code in preparation of ttm_tt & backend merge.
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
---
drivers/gpu/d
From: Jerome Glisse
Split btw highmem and lowmem page was rendered useless by the
pool code. Remove it. Note further cleanup would change the
ttm page allocation helper to actualy take an array instead
of relying on list this could drasticly reduce the number of
function call in the common case o
From: Jerome Glisse
This field is not use by any of the driver just drop it.
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
---
drivers/gpu/drm/radeon/radeon_ttm.c |1 -
include/drm/ttm/ttm_bo_driver.h |2 --
2 files changed, 0 insertions(+), 3 deletions(-)
diff
From: Jerome Glisse
On failure we need to make sure the page we free has wb cache
attribute. Do this pas call the proper ttm page helper function.
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
---
drivers/gpu/drm/ttm/ttm_tt.c |5 -
1 files changed, 4 insertions(+), 1
From: Jerome Glisse
Use the ttm_tt page ptr array for page allocation, move the list to
array unwinding into the page allocation functions.
V2 split the fix to use ttm put page as a separate fix
properly fill pages array when TTM_PAGE_FLAG_ZERO_ALLOC is not
set
V3 Added back page_count()==1 chec
From: Jerome Glisse
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
---
drivers/gpu/drm/ttm/ttm_tt.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 2dd45ca..58ea7dc 100644
--- a/drivers
From: Jerome Glisse
ttm_backend will exist only and only with a ttm_tt, and ttm_tt
will be of interesting use only when bind to a backend. Thus to
avoid code & data duplication btw the two merge them.
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
---
drivers/gpu/drm/nouveau/
From: Jerome Glisse
Move the page allocation and freeing to driver callback and
provide ttm code helper function for those.
Most intrusive change, is the fact that we now only fully
populate an object this simplify some of code designed around
the page fault design.
Signed-off-by: Jerome Glisse
From: Konrad Rzeszutek Wilk
In TTM world the pages for the graphic drivers are kept in three different
pools: write combined, uncached, and cached (write-back). When the pages
are used by the graphic driver the graphic adapter via its built in MMU
(or AGP) programs these pages in. The programming
From: Konrad Rzeszutek Wilk
As a mechanism to detect whether SWIOTLB is enabled or not.
We also fix the spelling - it was swioltb instead of
swiotlb.
CC: FUJITA Tomonori
[v1: Ripped out swiotlb_enabled]
Signed-off-by: Konrad Rzeszutek Wilk
---
drivers/xen/swiotlb-xen.c |2 +-
include/linu
From: Konrad Rzeszutek Wilk
With the exception that we do not handle the AGP case. We only
deal with PCIe cards such as ATI ES1000 or HD3200 that have been
detected to only do DMA up to 32-bits.
CC: Dave Airlie
CC: Alex Deucher
Signed-off-by: Konrad Rzeszutek Wilk
Reviewed-by: Jerome Glisse
From: Konrad Rzeszutek Wilk
If the card is capable of more than 32-bit, then use the default
TTM page pool code which allocates from anywhere in the memory.
Note: If the 'ttm.no_dma' parameter is set, the override is ignored
and the default TTM pool is used.
CC: Ben Skeggs
CC: Francisco Jerez
So i did an overhaul of ttm_memory, i believe the simplification i did
make sense. See patch 5 for a longer explanation.
Thomas with the ttm_memory change the allocation of pages won't happen
if the accounting report that we are going over the limit and bo shrinker
failed to free any memory to mak
From: Jerome Glisse
This was never use in none of the driver, properly using userspace
page for bo would need more code (vma interaction mostly). Removing
this dead code in preparation of ttm_tt & backend merge.
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
Reviewed-by: Thoma
From: Jerome Glisse
Split btw highmem and lowmem page was rendered useless by the
pool code. Remove it. Note further cleanup would change the
ttm page allocation helper to actualy take an array instead
of relying on list this could drasticly reduce the number of
function call in the common case o
From: Jerome Glisse
This field is not use by any of the driver just drop it.
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/radeon/radeon_ttm.c |1 -
include/drm/ttm/ttm_bo_driver.h |2 --
2 files changed, 0 inser
From: Jerome Glisse
On failure we need to make sure the page we free has wb cache
attribute. Do this pas call the proper ttm page helper function.
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/ttm/ttm_tt.c |5 -
1 fi
From: Jerome Glisse
This is an overhaul of the ttm memory accounting. This tries to keep
the same global behavior while removing the whole zone concept. It
keeps a distrinction for dma32 so that we make sure that ttm don't
starve the dma32 zone.
There is 3 threshold for memory allocation :
- max
From: Jerome Glisse
Use the ttm_tt page ptr array for page allocation, move the list to
array unwinding into the page allocation functions.
V2 split the fix to use ttm put page as a separate fix
properly fill pages array when TTM_PAGE_FLAG_ZERO_ALLOC is not
set
V3 Added back page_count()==1 chec
From: Jerome Glisse
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/ttm/ttm_tt.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 303bbb
From: Jerome Glisse
ttm_backend will exist only and only with a ttm_tt, and ttm_tt
will be of interesting use only when bind to a backend. Thus to
avoid code & data duplication btw the two merge them.
V2 Rebase on top of memory accountign overhaul
Signed-off-by: Jerome Glisse
Reviewed-by: Konr
From: Jerome Glisse
Move the page allocation and freeing to driver callback and
provide ttm code helper function for those.
Most intrusive change, is the fact that we now only fully
populate an object this simplify some of code designed around
the page fault design.
V2 Rebase on top of memory a
From: Konrad Rzeszutek Wilk
As a mechanism to detect whether SWIOTLB is enabled or not.
We also fix the spelling - it was swioltb instead of
swiotlb.
CC: FUJITA Tomonori
[v1: Ripped out swiotlb_enabled]
Signed-off-by: Konrad Rzeszutek Wilk
---
drivers/xen/swiotlb-xen.c |2 +-
include/linu
From: Konrad Rzeszutek Wilk
With the exception that we do not handle the AGP case. We only
deal with PCIe cards such as ATI ES1000 or HD3200 that have been
detected to only do DMA up to 32-bits.
V2 force dma32 if we fail to set bigger dma mask
CC: Dave Airlie
CC: Alex Deucher
Signed-off-by: K
From: Konrad Rzeszutek Wilk
If the card is capable of more than 32-bit, then use the default
TTM page pool code which allocates from anywhere in the memory.
Note: If the 'ttm.no_dma' parameter is set, the override is ignored
and the default TTM pool is used.
V2 use pci_set_consistent_dma_mask
This apply on top of the ttm_tt & backend merge patchset.
Cheers,
Jerome
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From: Jerome Glisse
Move dma data to a superset ttm_dma_tt structure which herit
from ttm_tt. This allow driver that don't use dma functionalities
to not have to waste memory for it.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 18 +
drivers/gpu/drm/nou
So squeezed all to avoid any memory accouting messing, seems to work ok
so far.
Cheers,
Jerome
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From: Konrad Rzeszutek Wilk
As a mechanism to detect whether SWIOTLB is enabled or not.
We also fix the spelling - it was swioltb instead of
swiotlb.
CC: FUJITA Tomonori
[v1: Ripped out swiotlb_enabled]
Signed-off-by: Konrad Rzeszutek Wilk
---
drivers/xen/swiotlb-xen.c |2 +-
include/linu
From: Jerome Glisse
This was never use in none of the driver, properly using userspace
page for bo would need more code (vma interaction mostly). Removing
this dead code in preparation of ttm_tt & backend merge.
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
Reviewed-by: Thoma
From: Jerome Glisse
Split btw highmem and lowmem page was rendered useless by the
pool code. Remove it. Note further cleanup would change the
ttm page allocation helper to actualy take an array instead
of relying on list this could drasticly reduce the number of
function call in the common case o
From: Jerome Glisse
This field is not use by any of the driver just drop it.
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/radeon/radeon_ttm.c |1 -
include/drm/ttm/ttm_bo_driver.h |2 --
2 files changed, 0 inser
From: Jerome Glisse
On failure we need to make sure the page we free has wb cache
attribute. Do this pas call the proper ttm page helper function.
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/ttm/ttm_tt.c |5 -
1 fi
From: Jerome Glisse
Signed-off-by: Jerome Glisse
Reviewed-by: Konrad Rzeszutek Wilk
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/ttm/ttm_tt.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 3fb4c6
From: Jerome Glisse
Use the ttm_tt pages array for pages allocations, move the list
unwinding into the page allocation functions.
Signed-off-by: Jerome Glisse
---
drivers/gpu/drm/ttm/ttm_page_alloc.c | 85 +-
drivers/gpu/drm/ttm/ttm_tt.c | 36 +++
From: Jerome Glisse
Move the page allocation and freeing to driver callback and
provide ttm code helper function for those.
Most intrusive change, is the fact that we now only fully
populate an object this simplify some of code designed around
the page fault design.
V2 Rebase on top of memory a
From: Jerome Glisse
ttm_backend will exist only and only with a ttm_tt, and ttm_tt
will be of interesting use only when bind to a backend. Thus to
avoid code & data duplication btw the two merge them.
V2 Rebase on top of memory accounting overhaul
V3 Rebase on top of more memory accounting chang
From: Konrad Rzeszutek Wilk
In TTM world the pages for the graphic drivers are kept in three different
pools: write combined, uncached, and cached (write-back). When the pages
are used by the graphic driver the graphic adapter via its built in MMU
(or AGP) programs these pages in. The programming
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