Re: Update: UVD status on loongson 3a platform

2013-09-05 Thread cee1
gt; >> Cheers, >> Jerome > > Also it might be that you can't do write combining on your platform, > which would be a major drawback as it's assume by radeon userspace. > I would need to check the pcie specification, but write combining is > probably not mandatory

Re: Update: UVD status on loongson 3a platform

2013-09-05 Thread cee1
nto user process mapping ? ie do you have > something like Intel PAT or something like MTRR or something else. > > In other word, can you map into process address space a region of > io memory (GPU VRAM in this case) and mark it as uncached so that > none of the access to it goes thro