compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Correct the misspell in commit message. (Krzysztof)
Changes in v4:
- Separate all DTS changes to a separate patch. (Krzysztof)
Changes in v3
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)
Changes
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
flag. (Thierry)
Changes in
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Remove "reg" D
re the clock framework shuts of unused clocks
> (including the aclk).
>
> While there also switch to doing prepare and enable in one step rather
> then separate steps to reduce the amount of code required.
>
> Signed-off-by: Sjoerd Simons
Looks good and test on chromeos-3.14 tree, no
On 09/29/2015 05:55 PM, Yakir Yang wrote:
>
>
> On 09/29/2015 05:28 PM, Sjoerd Simons wrote:
>> When doing the initial setup both the hclk and the aclk need to be
>> enabled otherwise the board will simply hang. This only occurs when
>> building the vop driver as a mo
Hi Krzysztof,
On 09/30/2015 01:17 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:29, Yakir Yang wrote:
>> Split the dp core driver from exynos directory to bridge directory,
>> and rename the core driver to analogix_dp_*, rename the platform
>> code to exynos_dp.
Hi Krzysztof,
On 09/30/2015 01:22 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:34, Yakir Yang wrote:
>> Fix some obvious alignment problems, like alignment and line
>> over 80 characters problems, make this easy to be maintained
>> later.
>>
>> Signed-off-by:
Hi Krzysztof,
On 09/30/2015 01:39 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:43, Yakir Yang wrote:
>> After exynos_dp have been split the common IP code into analogix_dp driver,
>> the analogix_dp driver have deprecated some Samsung platform properties which
>> could
Hi Krzysztof,
On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:37, Yakir Yang wrote:
>> Both hsync/vsync polarity and interlace mode can be parsed from
>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>> by the video code.
>>
>
Hi Krzysztof,
On 09/30/2015 03:34 PM, Krzysztof Kozlowski wrote:
> On 30.09.2015 16:19, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
>>> On 22.09.2015 16:37, Yakir Yang wrote:
>>>> Both hsync/vsync pola
Hi Krzysztof,
On 09/30/2015 04:26 PM, Krzysztof Kozlowski wrote:
> On 30.09.2015 17:20, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> On 09/30/2015 03:34 PM, Krzysztof Kozlowski wrote:
>>> On 30.09.2015 16:19, Yakir Yang wrote:
>>>> Hi Krzysztof,
>>>
Hi Daniel,
On 03/31/2016 06:15 PM, Daniel Vetter wrote:
> On Mon, Feb 15, 2016 at 07:08:05PM +0800, Yakir Yang wrote:
>> Hi all,
>>
>>The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>> share the same IP, so a lot of parts can be re-used. I sp
8e3ae23b22626d9a7c72a760b55fc:
>
> drm: bridge: analogix/dp: Fix the possible dead lock in bridge
> disable time (2016-03-29 11:09:45 +0800)
>
> ----
> Heiko Stuebner (2):
> drm/exynos: dp: rename implementatio
On 04/01/2016 12:02 AM, Doug Anderson wrote:
> Hi,
>
> On Thu, Mar 31, 2016 at 2:56 AM, Thierry Reding wrote:
>> Ugh... most of these functions shouldn't be there in the first place. We
>> have helpers in the core that already do this. Most of the functionality
>> is duplicated in this driver.
>>
Hi Guenter
On 03/31/2016 04:32 AM, Guenter Roeck wrote:
> Hi,
>
> On Mon, Feb 15, 2016 at 07:09:36PM +0800, Yakir Yang wrote:
>> Split the dp core driver from exynos directory to bridge directory,
>> and rename the core driver to analogix_dp_*, rename the platform
Hi Dan,
On 04/07/2016 03:41 AM, Dan Carpenter wrote:
> Hello Yakir Yang,
>
> The patch 7b4b7a8db439: "drm: bridge: analogix/dp: Fix the possible
> dead lock in bridge disable time" from Feb 15, 2016, leads to the
> following static checker warning:
>
>
at
just need to assign all hotplug enum with no-zero values.
Reported-by: Dan Carpenter
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
b/
Sorry for disturb, I make a mistaken about the
receive list, please ignore this email.
- Yakir
On 04/07/2016 12:15 PM, Yakir Yang wrote:
> The enum value of DP_IRQ_TYPE_HP_CABLE_IN is zero, but driver only
> send drm hp event when the irq_type and the enum value is true.
>
>
at
just need to assign all hotplug enum with no-zero values.
Reported-by: Dan Carpenter
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
b/
On 04/13/2016 01:38 PM, Jingoo Han wrote:
> On Tuesday, April 05, 2016 11:46 AM, Yakir Yang wrote:
>> Hi David,
>>
>> This v2 pull request just fixed the module compiled failed problem which
>> pointed by Guenter,
>> detail relate to [1]
>>
>> Thanks
ANALOGIX_DP_PLL_REG_1
Yakir Yang (8):
drm: bridge: analogix_dp: rename RK3288_DP to ROCKCHIP_DP
drm: rockchip: analogix_dp: split the lcdc select setting into device
data
drm/rockchip: analogix_dp: add rk3399 eDP support
drm: bridge: analogix_dp: correct the register bit define error in
Rename RK3288_DP marcos to ROCKCHIP_DP, prepare to add eDP
support for more Rockchip chips.
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 4 ++--
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 6 +++---
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
eDP controller need to declare which vop provide the video source,
and it's defined in GRF registers.
But different chips have different GRF register address, so we need to
create a device data to declare the GRF messages for each chips.
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/roc
RK3399 and RK3288 shared the same eDP IP controller, only some light
difference with VOP configure and GRF configure.
Signed-off-by: Yakir Yang
---
.../bindings/display/bridge/analogix_dp.txt| 1 +
.../display/rockchip/analogix_dp-rockchip.txt | 2 +-
drivers/gpu/drm/rockchip
There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special
registers setting").
The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1
BIT 0, not BIT 1.
Signed-off
Some boards don't need to declare a panel device node, like the
display interface is DP monitors, so it's necessary to make the
panel detect to an optional action.
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 48 -
1 file c
It's helpful to expand the mode_valid callback to platform driver,
so they could valid the display mode or information.
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 15 +++
include/drm/bridge/analogix_dp.h | 4
2
Rockchip VOP couldn't output YUV video format for eDP controller, so
when driver detect connector support YUV video format, we need to hack
it down to RGB888.
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 19 +++
1 file changed, 19 inser
at
just need to assign all hotplug enum with no-zero values.
Reported-by: Dan Carpenter
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
b/
Panel regulator is controller by a normal GPIO, so we need to
write a regulator-fixed node for it.
Signed-off-by: Yakir Yang
---
arch/arm/boot/dts/rk3288-evb-act8846.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts
b/arch/arm/boot/dts/rk3288
The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and
32 pins eDP interface. This module supports 1536x2048 mode.
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/panel/panel-simple.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gp
Panel regulator is controller by a normal GPIO, so we need to
write a regulator-fixed node for it.
Signed-off-by: Yakir Yang
---
arch/arm/boot/dts/rk3288-evb-rk808.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts
b/arch/arm/boot/dts/rk3288-evb
Rob,
On 06/29/2016 04:59 AM, Rob Herring wrote:
> On Tue, Jun 28, 2016 at 12:51:12PM +0800, Yakir Yang wrote:
>> The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and
>> 32 pins eDP interface. This module supports 1536x2048 mode.
>>
&g
Doug,
On 06/23/2016 01:17 PM, Doug Anderson wrote:
> Hi,
>
> On Wed, Jun 22, 2016 at 6:47 PM, Yakir Yang wrote:
>> The document about rockchip platform make a mistaken in available
>> compatible name of "rk3288-edp", we should correct it to "rk3288-dp"
&
Doug,
On 06/23/2016 01:16 PM, Doug Anderson wrote:
> Yakir,
>
> On Wed, Jun 22, 2016 at 6:58 PM, Yakir Yang wrote:
>> For RK3399's GRF module, if we want to operate the graphic related grf
>> registers, we need to enable the pclk_vio_grf which supply power for VIO
>
Sean,
On 06/23/2016 10:24 PM, Sean Paul wrote:
> On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang wrote:
>> The enum value of DP_IRQ_TYPE_HP_CABLE_IN is zero, but driver only
>> send drm hp event when the irq_type and the enum value is true.
>>
>> if (irq_typ
Sean,
On 06/23/2016 10:19 PM, Sean Paul wrote:
> On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang wrote:
>> Rockchip VOP couldn't output YUV video format for eDP controller, so
>> when driver detect connector support YUV video format, we need to hack
>> it down to RGB888.
Sean,
On 06/23/2016 10:22 PM, Sean Paul wrote:
> On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang wrote:
>> The hardware IC designed that VOP must output the RGB10 video format to
>> eDP contoller, and if eDP panel only support RGB8, then eDP contoller
>> should cut down the vi
Sean,
On 06/23/2016 10:10 PM, Sean Paul wrote:
> On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang wrote:
>> Some boards don't need to declare a panel device node, like the
>> display interface is DP monitors, so it's necessary to make the
>> panel detect to an optio
Sean,
On 06/23/2016 09:48 PM, Sean Paul wrote:
> On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang wrote:
>> RK3399 and RK3288 shared the same eDP IP controller, only some light
>> difference with VOP configure and GRF configure.
>>
>> Signed-off-by: Yakir
Heiko & Sean
On 06/24/2016 12:16 AM, Heiko Stuebner wrote:
> Am Donnerstag, 23. Juni 2016, 10:32:53 schrieb Sean Paul:
>> On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang wrote:
>>> eDP controller need to declare which vop provide the video source,
>>> and it's d
Sean,
On 06/23/2016 10:33 PM, Sean Paul wrote:
> On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang wrote:
>> There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
>> by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special
>> reg
Sean,
On 06/23/2016 09:27 PM, Sean Paul wrote:
> On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang wrote:
>> As vendor document indicate, when REF_CLK bit set 0, then DP
>> phy's REF_CLK should switch to 24M source clock.
>>
>> But due to IC PHY layout mistaken, som
[https://chromium-review.googlesource.com/#/c/346319/15]
- Add tested flag from Javier
- Add this patch in v3
- Add this patch in v3
Yakir Yang (11):
drm/rockchip: analogix_dp: split the lcdc select setting into device
data
drm/bridge: analogix_dp: correct the register bit define
eDP controller need to declare which vop provide the video source,
and it's defined in GRF registers.
But different chips have different GRF register address, so we need to
create a device data to declare the GRF messages for each chips.
Signed-off-by: Yakir Yang
Acked-by: Mark Yao
Review
ake this little hack.
Signed-off-by: Yakir Yang
Reviewed-by: Tomasz Figa
Tested-by: Javier Martinez Canillas
---
Changes in v4:
- Remove subdev_type number, and add 'is_rockchip(type)' helper function (Sean)
- Add reviewed flag from Tomasz.
Changes in v3:
- Make this hack code more c
There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special
registers setting").
The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1
BIT 0, not BIT 1.
Signed-off-by: Yakir Ya
RK3399 and RK3288 shared the same eDP IP controller, only some light
difference with VOP configure and GRF configure.
Signed-off-by: Yakir Yang
Acked-by: Mark Yao
Reviewed-by: Tomasz Figa
---
Changes in v4:
- Improved the overly complicated .atomic_check function. (Sean)
- Add reviewed flag
Some boards don't need to declare a panel device node, like the
display interface is DP monitors, so it's necessary to make the
panel detect to an optional action.
Signed-off-by: Yakir Yang
Acked-by: Mark Yao
Reviewed-by: Tomasz Figa
---
Changes in v4:
- Move of_node_put(panel_node
It's better to pass the connector to platform driver in .get_modes()
callback, just like what the .get_modes() helper function designed.
Signed-off-by: Yakir Yang
Reviewed-by: Sean Paul
Reviewed-by: Tomasz Figa
---
Changes in v4:
- Add reviewed flag from Sean.
- Add reviewed flag from T
Rockchip VOP couldn't output YUV video format for eDP controller, so
when driver detect connector support YUV video format, we need to hack
it down to RGB888.
Signed-off-by: Yakir Yang
Acked-by: Mark Yao
Reviewed-by: Tomasz Figa
---
Changes in v4:
- Using mask variable to collect the YUV
The hardware IC designed that VOP must output the RGB10 video format to
eDP contoller, and if eDP panel only support RGB8, then eDP contoller
should cut down the video data, not via VOP contoller, that's why we need
to hardcode the VOP output mode to RGA10 here.
Signed-off-by: Yakir Yang
at
just need to assign all hotplug enum with no-zero values.
Reported-by: Dan Carpenter
Signed-off-by: Yakir Yang
Reviewed-by: Sean Paul
Reviewed-by: Stéphane Marchesin
Reviewed-by: Tomasz Figa
Tested-by: Javier Martinez Canillas
---
Changes in v4:
- Add reviewed flag from Sean.
- Add review
For RK3399's GRF module, if we want to operate the graphic related grf
registers, we need to enable the pclk_vio_grf which supply power for VIO
GRF IOs, so it's better to introduce an optional grf clock in driver.
Signed-off-by: Yakir Yang
Reviewed-by: Douglas Anderson
Reviewed-by: T
t for rockchip variant of analogix_dp").
Reported-by: Tomasz Figa
Signed-off-by: Yakir Yang
Reviewed-by: Douglas Anderson
Reviewed-by: Tomasz Figa
---
Changes in v4:
- Add reviewed flag from Doug.
- Add reviewed flag from Tomasz.
Changes in v3:
- Add this patch in v3
.../devicetree/binding
Kuninori,
On 06/24/2016 10:40 AM, Kuninori Morimoto wrote:
> From: Kuninori Morimoto
>
> Current dw-hdmi is supporting sound via AHB bus, but it has
> I2S audio feature too. This patch adds I2S audio support to dw-hdmi.
> This HDMI I2S is supported by using ALSA SoC common HDMI encoder
> driver.
Sean,
On 06/29/2016 10:01 PM, Sean Paul wrote:
> On Wed, Jun 29, 2016 at 5:14 AM, Yakir Yang wrote:
>> RK3399 and RK3288 shared the same eDP IP controller, only some light
>> difference with VOP configure and GRF configure.
>>
> The whole set looks good to me. All patche
Exynos G2D driver, it only manages the
command lists received from user, so user should make the command list
to data and registers needed by operation to use.
I have prepared an userspace demo application for testing:
https://github.com/yakir-Yang/libdrm-rockchip
That is a rockchip libdrm
Introduce a common subdrv register/unregister interfaces, help
external driver to hook the drm open/close event.
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 49 +
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 15 +
2 files
IP_RGA_EXEC: execute the command lists setted to driver
Signed-off-by: Yakir Yang
---
.../bindings/display/rockchip/rockchip-rga.txt | 36 +
drivers/gpu/drm/rockchip/Kconfig | 9 +
drivers/gpu/drm/rockchip/Makefile | 1 +
drivers/gpu/drm/rockchip/rockchip_dr
This patch add the RGA dt config of rk3288 SoC.
Signed-off-by: Yakir Yang
---
arch/arm/boot/dts/rk3288.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 8ac49f3..af948b9 100644
--- a/arch/arm/boot/dts
Signed-off-by: Yakir Yang
---
arch/arm/boot/dts/rk3288-veyron.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi
b/arch/arm/boot/dts/rk3288-veyron.dtsi
index 9fce91f..5eb4e97 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts
Hi Heiko,
On 03/21/2016 07:29 PM, Heiko Stübner wrote:
> Hi Yakir,
>
> Am Montag, 21. März 2016, 17:28:38 schrieb Yakir Yang:
>> This patch set would add the RGA direct rendering based 2d graphics
>> acceleration module.
> very cool to see that.
;)
>> This patch
Hi Heiko,
On 03/22/2016 08:42 AM, Heiko Stuebner wrote:
> Hi Yakir,
>
> Am Montag, 21. März 2016, 20:17:46 schrieb Yakir Yang:
>> On 03/21/2016 07:29 PM, Heiko Stübner wrote:
>>> Am Montag, 21. März 2016, 17:28:38 schrieb Yakir Yang:
>>>> This patch set woul
On 03/22/2016 08:41 PM, Dave Airlie wrote:
>>> So although it's small framework or just subdirectory, we would need
>>> someone who can manage the framework to avoid further confusion if
>>> necessary.
>> So maybe it just doesn't need a maintainer, and maybe those the owner
>> of the bridge driver
Heiko Stuebner (2):
drm/exynos: dp: rename implementation specific driver part
drm: bridge: analogix/dp: rename register constants
Yakir Yang (15):
drm: bridge: analogix/dp: split exynos dp driver to bridge directory
drm: bridge: analogix/dp: fix some obvious code style
t;>>> Am Montag, 21. März 2016, 20:17:46 schrieb Yakir Yang:
>>>>> On 03/21/2016 07:29 PM, Heiko Stübner wrote:
>>>>>> Am Montag, 21. März 2016, 17:28:38 schrieb Yakir Yang:
>>>>>>> This patch set would add the RGA direct rendering ba
Hi Emil,
On 03/28/2016 08:21 PM, Emil Velikov wrote:
> On 22 March 2016 at 00:42, Heiko Stuebner wrote:
>> Hi Yakir,
>>
>> Am Montag, 21. März 2016, 20:17:46 schrieb Yakir Yang:
>>> On 03/21/2016 07:29 PM, Heiko Stübner wrote:
>>>> Am Montag, 2
Hi Andreas,
On 03/22/2016 06:24 PM, Andreas Färber wrote:
> Hi Yakir,
>
> Am 21.03.2016 um 13:17 schrieb Yakir Yang:
>> On 03/21/2016 07:29 PM, Heiko Stübner wrote:
>>> Am Montag, 21. März 2016, 17:28:38 schrieb Yakir Yang:
>>>> This patch set would a
Hi Rob,
+ rockchip / dri email list back
On 03/23/2016 10:20 PM, Rob Herring wrote:
> On Mon, Mar 21, 2016 at 05:40:06PM +0800, Yakir Yang wrote:
>> Rockchip RGA is a separate 2D raster graphic acceleration unit. It
>> accelerates 2D graphics operations, such as point/line
Adds a sound driver that combines rockchip-i2s cpu_dai and dw-hdmi-codec
as codec_dai to provide hdmi audio output on rk3288 platforms.
Signed-off-by: Yakir Yang
---
sound/soc/rockchip/Kconfig | 9 ++
sound/soc/rockchip/Makefile | 2 +
sound/soc/rockchip
creat dw-hdmi-audio device in probe function, and support
some interfaces to dw-hdmi-audio driver for setting hdmi
audio format.
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/bridge/dw_hdmi.c | 28
include/drm/bridge/dw_hdmi.h | 12
2 files changed
support
see https://patchwork.kernel.org/patch/5442361/
Yakir Yang (6):
drm: bridge/dw_hdmi: add hdmi audio config interfaces
drm: bridge/bridge: add support for rk3288 hdmi-audio
ASoC: dw-hdmi-audio: add codec driver for dw hdmi audio
ASoC: rockchip-hdmi-audio: add sound driver for hdmi audio
codec driver get some interfaces from dw_hdmi driver, than using those
to set hdmi audio formats, corresponding to alsa formats.
Signed-off-by: Yakir Yang
---
sound/soc/codecs/Kconfig | 4 +
sound/soc/codecs/Makefile| 2 +
sound/soc/codecs/dw-hdmi-audio.c | 371
]â value that should be outputted by the
Audio
Packetizer.
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/bridge/dw_hdmi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c
index 9ba96de..0c19276 100644
--
Required properties:
- compatible: platform specific
- cpu-of-node: the device node of cpu_dai
- codec-name: the dw-hdmi codec's device name
- codec-dai-name: the dw-hdmi codec's dai name
Signed-off-by: Yakir Yang
---
.../bindings/sound/rockchip,rockchip-hdmi-audio.txt
Add hdmi_audio to rk3288.dtsi, enable hdmi_audio in rk3288-evb.dts
Signed-off-by: Yakir Yang
series-cc: Dominik Behr
---
arch/arm/boot/dts/rk3288-evb.dtsi | 11 +++
arch/arm/boot/dts/rk3288.dtsi | 8
2 files changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts
å¨ 2015/3/2 17:15, Paul Bolle åé:
> On Sat, 2015-02-28 at 21:59 -0500, Yakir Yang wrote:
>> --- /dev/null
>> +++ b/sound/soc/codecs/dw-hdmi-audio.c
>> @@ -0,0 +1,379 @@
>> +/*
>> + * dw-hdmi-codec.c
> Doesn't match the filename. Is this line needed
å¨ 2015/3/2 17:07, Paul Bolle åé:
> On Sat, 2015-02-28 at 22:04 -0500, Yakir Yang wrote:
>> --- /dev/null
>> +++ b/sound/soc/rockchip/rockchip_hdmi_audio.c
>> @@ -0,0 +1,169 @@
>> +/*
>> + * rockchip-hdmi-card.c
> Doesn't match the filename. Is this
s.
- For pixel clock less than 74.25MHz, set txlvl to 19 and set cklvl to 18.
Yakir Yang (3):
drm: bridge/dw_hdmi: fixed codec style
drm: bridge/dw_hdmi_rockchip: improve hdmi eye-diagram test
drm: bridge/dw_hdmi: improve hdmi single-end test
drivers/gpu/drm/bridge/dw_hdmi.c
dw_hdmi_plat_data *plat_data = hdmi->plat_data;
+ const struct dw_hdmi_mpll_config *mpll_config = plat_data->mpll_cfg;
+ const struct dw_hdmi_curr_ctrl *curr_ctrl = plat_data->cur_ctr;
+ const struct dw_hdmi_sym_term *sym_term = plat_data->sym_term;
Signed-off-by: Yakir Yang
---
Cha
l
should set to 18, txlvl should set to 19.
Signed-off-by: Yakir Yang
---
Changes in v2:
- For pixel clock less than 74.25MHz, set txlvl to 19 and set cklvl to 18.
drivers/gpu/drm/bridge/dw_hdmi.c| 14 +++---
drivers/gpu/drm/imx/dw_hdmi-imx.c | 12 ++--
dri
et to 18(2.80v), and
txlvl set to 19(2.75v).
Signed-off-by: Yakir Yang
---
Changes in v3:
- For pixel clock less than 148.5MHz, set txlvl to 20.
Changes in v2:
- For pixel clock less than 74.25MHz, set txlvl to 19 and set cklvl to 18.
drivers/gpu/drm/bridge/dw_hdmi.c
s.
- For pixel clock less than 74.25MHz, set txlvl to 19 and set cklvl to 18.
Yakir Yang (3):
drm: bridge/dw_hdmi: fixed codec style
drm: bridge/dw_hdmi_rockchip: improve hdmi eye-diagram test
drm: bridge/dw_hdmi: improve hdmi single-end test
drivers/gpu/drm/bridge/dw_hdmi.c
As for 1920x1080 display resolution, we should turn on the
Transmitter Trailer-B.
Signed-off-by: Yakir Yang
---
Changes in v2:
- Set slopeboost back to 10%-20%, then rasing/falling time would pass.
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
, set txlvl to 20.
Changes in v2:
- Set slopeboost back to 10%-20%, then rasing/falling time would pass.
- For pixel clock less than 74.25MHz, set txlvl to 19 and set cklvl to 18.
Yakir Yang (3):
drm: bridge/dw_hdmi: fixed codec style
drm: bridge/dw_hdmi_rockchip: improve hdmi eye-diagram test
Using a local struct pointer to reduce one level of indirection
makes the code slightly more readable.
Signed-off-by: Yakir Yang
Reviewed-by: Daniel Kurtz
---
Changes in v3:
- make commit message more readable
Changes in v2: None
drivers/gpu/drm/bridge/dw_hdmi.c | 8
1 file changed
As for 1920x1080 display resolution, we should turn on the
Transmitter Trailer-B.
Signed-off-by: Yakir Yang
---
Changes in v3: None
Changes in v2:
- Set slopeboost back to 10%-20%, then rasing/falling time would pass.
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +-
1 file changed, 1
Because of iMX6 & Rockchip have differnet mpll config parameter,
the VLEVCTRL parameter would be different. In this case we should
separate VLEVCTRL setting from the common dw_hdmi driver, config
this parameter in platform driver(dw_hdmi-imx and dw_hdmi-rockchip)
Signed-off-by: Yakir
2:
- set slopeboost back to 10%-20%, then rasing/falling time would pass.
- for pixel clock less then 74.25MHz, set txlvl to 19 and cklvl to 18.
Yakir Yang (3):
drm: bridge/dw_hdmi: fixed codec style
drm: bridge/dw_hdmi: separate VLEVCTRL settting into platform driver
drm: rockchip/dw_hdmi-
When pixel clock less than 148.5MHz, make sloopboost=2 tklvl=20
cklvl=13 increase rasing/falling time and increase data & clock
voltage driver.
When pixel clock less than 74.25MHz, make sloopboost=0 tklvl=19
cklvl=18, increase data and clock voltage driver.
Signed-off-by: Yakir Yang
---
Cha
Using a local struct pointer to reduce one level of indirection
makes the code slightly more readable.
Signed-off-by: Yakir Yang
Reviewed-by: Daniel Kurtz
---
Changes in v4: None
Changes in v3:
- make commit message more readable
Changes in v2: None
drivers/gpu/drm/bridge/dw_hdmi.c | 8
On 11/13/2015 07:38 AM, Rob Herring wrote:
> On Thu, Nov 12, 2015 at 09:27:21AM +0800, Yakir Yang wrote:
>> Hi Rob,
>>
>> On 11/12/2015 07:10 AM, Rob Herring wrote:
>>> On Fri, Oct 30, 2015 at 09:09:15AM +0800, Yakir Yang wrote:
>>>> Some edp screen do no
Hi Brian,
Thank you for debugging, and fell sorry for the delay reply
On 11/06/2015 07:45 AM, Brian Norris wrote:
> Hi,
>
> A few updates:
>
> On Tue, Nov 03, 2015 at 05:13:48PM -0800, Brian Norris wrote:
>> On Wed, Nov 04, 2015 at 08:48:38AM +0800, Yakir Yang wrote:
>&
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v10:
- Fix the wrong macro value of GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK (Brian)
BIT(4) -> BIT
thout new changes but rebased on the latest kernel again and
again. If you thought those patches is fine, it would be very grateful to
give some ACKs to those changes.
Thanks,
- Yakir
On 10/28/2015 04:15 PM, Yakir Yang wrote:
> Hi all,
>
> The Samsung Exynos eDP controller and Rockchip RK3
atchwork.kernel.org/patch/7279801
[Rebased on] Vladimir Zapolskiy: https://patchwork.kernel.org/patch/7279801
Thanks
- Yakir
Sean Paul (1):
drm: Add Content Protection properties to drm
Yakir Yang (1):
drm: bridgw/dw_hdmi: add basic hdmi hdcp driver
drivers/gpu/d
e the the value with the KSV
(or similarly unique identifier, if not using HDCP) of the first-hop
device (sink or repeater).
Signed-off-by: Sean Paul
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/drm_crtc.c | 21 +
drivers/gpu/drm/drm_sysfs.c | 46 +++
des driver export an interface for specific platform
driver that used for passing the encrypted HDCP key.
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/bridge/dw_hdmi.c | 355 ---
drivers/gpu/drm/bridge/dw_hdmi.h | 20 +++
include/drm/bridge/dw_hdmi.h
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