_enable(struct drm_bridge *bridge)
> +{
> + struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
> + unsigned int val = 0;
here as well
> +static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
> +{
> + struct ti_sn_bridge *pdata = brid
defines would be better
> +static int wled_configure_short_irq(struct wled *wled,
> + struct platform_device *pdev)
> +{
> + int rc = 0, short_irq;
superfluous initialization of rc
--
~Vinod
On 17-08-21, 17:19, Chunfeng Yun wrote:
> Add support type switch by pericfg register between USB3, PCIe,
> SATA, SGMII, this is used to replace the way through efuse or
> jumper.
Applied all, thanks
--
~Vinod
arameters
> should cover all potential users.
>
> Cc: Kishon Vijay Abraham I
> Cc: Vinod Koul
> Cc: NXP Linux Team
> Reviewed-by: Robert Foss
> Signed-off-by: Liu Ying
> ---
> v3->v4:
> * Add Robert's R-b tag.
>
> v2->v3:
> * No change.
gt;
> [1]
> https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html#in-line-member-documentation-comments
It 'may be' but I would like all headers of a subsystem to display one
style. As I said linux/phy/phy.h use a style which we should use
everywhere.
Thanks
--
~Vinod
!
Droped the series now
--
~Vinod
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
| 3 +--
> drivers/dma/pl330.c | 3 +--
For dmaengine:
Acked-By: Vinod Koul
--
~Vinod
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
li
> Cc: Ray Jui
> Cc: Scott Branden
> Cc: Pavel Machek
> Cc: Ulf Hansson
> Cc: Kishon Vijay Abraham I
> Cc: Vinod Koul
> Cc: Geert Uytterhoeven
> Cc: Linus Walleij
> Cc: Daniel Lezcano
> Cc: linux-cry...@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
odule.
Applied, thanks
--
~Vinod
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
hy)
> > drvr_en = 0x10;
> > }
> >
> > - voltage_swing_cfg =
> > qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
> > - pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_leve
On 23-11-20, 11:46, Robert Foss wrote:
> 4k requires two dsi pipes, so don't report MODE_OK when only a
> single pipe is configured. But rather report MODE_PANEL to
> signal that requirements of the panel are not being met.
Acked-By: Vinod Koul
> Reported-by: Peter Collingbourn
On 17-11-20, 07:14, Chun-Kuang Hu wrote:
> mtk_mipi_dsi_phy is currently placed inside mediatek drm driver, but it's
> more suitable to place a phy driver into phy driver folder, so move
> mtk_mipi_dsi_phy driver into phy driver folder.
Acked-By: Vinod Koul
I am thinking this wou
mtk_hdmi_phy_driver is not declared as static, so statify it.
drivers/phy/mediatek/phy-mtk-hdmi.c:204:24: warning: symbol
'mtk_hdmi_phy_driver' was not declared. Should it be static?
Signed-off-by: Vinod Koul
---
drivers/phy/mediatek/phy-mtk-hdmi.c | 2 +-
1 file changed, 1 inser
return &mtk_hdmi_phy_dev_ops;
> >
> > - dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
> > - return NULL;
> > + if (hdmi_phy)
> > + dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
> &
comments raised by Dimitry
- Add dsc parameters calculation from downstream
Vinod Koul (11):
drm/msm/dsi: add support for dsc data
drm/msm/disp/dpu1: Add support for DSC
drm/msm/disp/dpu1: Add support for DSC in pingpong block
drm/msm/disp/dpu1: Add DSC support in RM
drm/msm/disp/dpu1: Add
Display Stream Compression (DSC) parameters need to be calculated. Add
helpers and struct msm_display_dsc_config in msm_drv for this
msm_display_dsc_config uses drm_dsc_config for DSC parameters.
Signed-off-by: Vinod Koul
---
Changes since RFC:
- Drop the DT parsing code
- Port dsc param
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Signed-off-by: Vinod Koul
---
Changes since RFC:
- Drop unused enums
drivers/gpu/drm/msm/Makefile | 1 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 13
In SDM845, DSC can be enabled by writing to pingpong block registers, so
add support for DSC in hw_pp
Signed-off-by: Vinod Koul
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 +++
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 14
2 files changed, 46 insertions
This add the bits in RM to enable the DSC blocks
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 32 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
3 files changed, 34 insertions(+)
diff --git a
This add SDM845 DSC blocks into hw_catalog
Signed-off-by: Vinod Koul
---
Changes since RFC:
- use BIT values from MASK
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 22 +++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b
Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1
We cannot enable mode_3d when we are using the DSC. So pass
configuration to detect DSC is enabled and not enable mode_3d
when we are using DSC
We add a helper dpu_encoder_helper_get_dsc_mode() to detect dsc
enabled and pass this to .setup_intf_cfg()
Signed-off-by: Vinod Koul
---
drivers/gpu
When DSC is enabled in DT, we need to configure the encoder for DSC
configuration, calculate DSC parameters for the given timing.
This patch adds that support by adding dpu_encoder_prep_dsc() which is
invoked when DSC is enabled in DT
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1
ed-by: Abhinav Kumar
Signed-off-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
Changes since RFC:
- Add more details in changelog
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/dr
When DSC is enabled, we need to configure DSI registers accordingly and
configure the respective stream compression registers.
Add support to calculate the register setting based on DSC params and
timing information and configure these registers.
Signed-off-by: Vinod Koul
---
drivers/gpu/drm
When DSC is enabled, we need to pass the DSC parameters to panel driver
as well, so add a dsc parameter in panel and set it when DSC is enabled
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 16 +++-
include/drm/drm_panel.h| 7 +++
2 files
reation to the
> > display driver - see how other uses drm_bridge_connector_init() to do so
> > - it is relatively simple.
> >
> > Should be doable - and reach out if you need some help.
Yes it is and doable and you find this at [1], would need a rebase
though.
> At some point I think Vino
On 02-11-20, 07:08, Chun-Kuang Hu wrote:
> + Vinod:
>
> Hi, Chunfeng:
>
> Chunfeng Yun 於 2020年10月30日 週五 下午2:24寫道：
> >
> > On Thu, 2020-10-29 at 23:27 +0800, Chun-Kuang Hu wrote:
> > > mtk_mipi_dsi_phy is currently placed inside mediatek drm driver, but it&
On 17-11-20, 00:17, Chun-Kuang Hu wrote:
> Hi, Vinod:
>
> Vinod Koul 於 2020年11月16日 週一 下午3:25寫道：
> >
> > On 02-11-20, 07:08, Chun-Kuang Hu wrote:
> > > + Vinod:
> > >
> > > Hi, Chunfeng:
> > >
> > > Chunfeng Yun 於 2020年10月30日 週五
property and set mdp clk during resume sequence.
- Add fixes tag.
Changes in v3:
- Remove extra line after fixes tag.(Stephen Boyd)
Fixes: 62fbdce91("arm64: dts: qcom: sc7280: add display dt nodes")
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/s
use max clock during probe/bind sequence from the opp table.
The clock will be scaled down when framework sends an update.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b
m8250.dtsi: add display system nodes")
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
ind
dm845: Add dpu to sdm845 dts file")
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
ind
c7180: add display dt nodes")
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index e1c46b
uency in opp
table"
Changes in v4:
- Add similar change for sm8250.(Dmitry)
Changes in v5:
- Add change to set mdp clk to max frequency in opp table during mdp probe/bind.
Vinod Polimera (5):
arm64/dts/qcom/sc7280: remove assigned-clock-rate property for mdp clk
arm64/dts/qcom/sc71
er.kernel.org; robdcl...@gmail.com;
> diand...@chromium.org; quic_kalyant
> Subject: Re: [PATCH v5 1/5] arm64/dts/qcom/sc7280: remove assigned-clock-
> rate property for mdp clk
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and d
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
This patch is dependent on below patch
https://patchwork.kernel.org/patch/12774067/
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 9
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
This patch is dependent on below patch
https://patchwork.kernel.org/patch/12774067/
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9
ncy in opp table during mdp probe/bind.
Changes in v6:
- Remove change log in dt patch.
- Fix the leak reference for opp by adding dev_pm_opp_put. (Dmitry)
Vinod Polimera (5):
drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table
during probe
arm64: dts: qcom: sm7280: remov
use max clock during probe/bind sequence from the opp table.
The clock will be scaled down when framework sends an update.
Fixes: 25fdd5933("drm/msm: Add SDM845 DPU support")
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
1 file changed, 8
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
This patch is dependent on below patch
https://patchwork.kernel.org/patch/12774067/
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
This patch is dependent on below patch
https://patchwork.kernel.org/patch/12774067/
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 9
of any links or attachments, and do not enable macros.
>
> On Tue, 8 Mar 2022 at 19:55, Vinod Polimera
> wrote:
> >
> > use max clock during probe/bind sequence from the opp table.
> > The clock will be scaled down when framework sends an update.
> >
> > Signe
>
> Hi,
>
> On Tue, Mar 8, 2022 at 8:55 AM Vinod Polimera
> wrote:
> >
> > use max clock during probe/bind sequence from the opp table.
> > The clock will be scaled down when framework sends an update.
> >
> > Signed-off-by: Vinod Polimera
>
> -Original Message-
> From: Doug Anderson
> Sent: Monday, March 14, 2022 7:28 PM
> To: dmitry.barysh...@linaro.org
> Cc: Vinod Polimera ; Stephen Boyd
> ; quic_vpolimer ;
> devicet...@vger.kernel.org; dri-devel@lists.freedesktop.org;
> freedr...@lists.fr
: Kalyan Thota
Signed-off-by: Vinod Polimera
---
arch/arm64/configs/defconfig | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 218 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 18 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 119
based on supported rotations for each hw.
Co-developed-by: Kalyan Thota
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 187 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 18 +++
drivers/gpu/drm/msm
based on supported rotations for each hw.
Changes in V5:
- update boolean value to true/false and add it for qcm2290.
Co-developed-by: Kalyan Thota
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 187
y
> of any links or attachments, and do not enable macros.
>
> Quoting Vinod Polimera (2022-03-14 07:46:53)
> > use max clock during probe/bind sequence from the opp table.
> > The clock will be scaled down when framework sends an update.
>
> Capitalize 'use'
2-git-send-email-quic_vpoli...@quicinc.com/
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
Reviewed-by: Douglas Anderson
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm6
2-git-send-email-quic_vpoli...@quicinc.com/
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
Reviewed-by: Douglas Anderson
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm6
2-git-send-email-quic_vpoli...@quicinc.com/
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
Reviewed-by: Douglas Anderson
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm6
want to transition it to kernel without underflowing.
The clock will be scaled down later when framework sends an update.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Douglas Anderson
---
drivers/gpu/dr
2-git-send-email-quic_vpoli...@quicinc.com/
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
Reviewed-by: Douglas Anderson
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm6
opp table
during mdp probe/bind.
Changes in v6:
- Remove change log in dt patch.
- Fix the leak reference for opp by adding dev_pm_opp_put. (Dmitry)
Changes in v7:
- Update commit message and fix tag. (Stephen/Doug)
Vinod Polimera (5):
drm/msm/disp/dpu1: set mdp clk to the maximum frequency in
On 17-02-22, 16:11, Marijn Suijten wrote:
> Hi Vinod,
>
> Thanks for taking time to go through this review, please find some
> clarifications below.
>
> On 2022-02-17 16:44:04, Vinod Koul wrote:
> > Hi Marijn,
> >
> > On 11-12-21, 01:03, Marijn Sui
: Kalyan Thota
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h| 21 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 185 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 18 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 109
On 22-03-22, 19:59, Marijn Suijten wrote:
> On 2022-03-22 22:46:50, Vinod Koul wrote:
> > On 17-02-22, 16:11, Marijn Suijten wrote:
> > > Hi Vinod,
> > >
> > > Thanks for taking time to go through this review, please find some
> > > clarifications belo
On 17-02-22, 22:44, Marijn Suijten wrote:
> On 2022-02-10 16:04:20, Vinod Koul wrote:
> > For DSC to work we typically need a 2,2,1 configuration. This should
> > suffice for resolutions up to 4k. For more resolutions like 8k this won't
> > work.
> >
> > A
On 17-02-22, 23:37, Marijn Suijten wrote:
> On 2022-02-10 16:04:20, Vinod Koul wrote:
> > For DSC to work we typically need a 2,2,1 configuration. This should
> > suffice for resolutions up to 4k. For more resolutions like 8k this won't
> > work.
> >
> > A
On 17-02-22, 23:32, Marijn Suijten wrote:
> On 2022-02-10 16:04:17, Vinod Koul wrote:
> > We need to configure the encoder for DSC configuration and calculate DSC
> > parameters for the given timing so this patch adds that support by
> > adding dpu_encoder_prep_dsc() which i
On 23-03-22, 20:10, Vinod Koul wrote:
> On 17-02-22, 23:32, Marijn Suijten wrote:
> > On 2022-02-10 16:04:17, Vinod Koul wrote:
> > > +
> > > + slice_count = dsc->drm->slice_count;
> > > + slice_per_intf = DIV_ROUND_UP(width, dsc->drm->slice_width);
On 21-02-22, 05:11, Dmitry Baryshkov wrote:
> On 10/02/2022 13:34, Vinod Koul wrote:
> > When DSC is enabled, we need to configure DSI registers accordingly and
> > configure the respective stream compression registers.
> >
> > Add support to calculate the register sett
On 17-02-22, 23:20, Marijn Suijten wrote:
> On 2022-02-10 16:04:16, Vinod Koul wrote:
> > Later gens of hardware have DSC bits moved to hw_ctl, so configure these
> > bits so that DSC would work there as well
> >
> > Reviewed-by: Dmitry Baryshkov
&g
Display Stream Compression (DSC) parameters need to be calculated. Add
helpers and struct msm_display_dsc_config in msm_drv for this
msm_display_dsc_config uses drm_dsc_config for DSC parameters.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers
(1):
drm/msm/dpu: don't use merge_3d if DSC merge topology is used
Vinod Koul (12):
drm/msm/dsi: add support for dsc data
drm/msm/dsi: Pass DSC params to drm_panel
drm/msm/disp/dpu1: Add support for DSC
drm/msm/disp/dpu1: Add support for DSC in pingpong block
drm/msm/disp/dpu1: A
: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
drivers/gpu/drm/msm/dsi/dsi.c | 5 +
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_host.c | 22 ++
drivers/gpu/drm/msm/msm_drv.h
In SDM845, DSC can be enabled by writing to pingpong block registers, so
add support for DSC in hw_pp
Reviewed-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 +++
.../gpu/drm/msm/disp/dpu1
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/Makefile | 1 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 13 ++
drivers/gpu/drm
This adds SDM845 DSC blocks into hw_catalog
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1
We need to configure the encoder for DSC configuration and calculate DSC
parameters for the given timing so this patch adds that support by
adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
igned-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 6 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 4 +++-
3 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/dr
Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++-
drivers/gpu/drm/msm/disp/dpu1
width.
The panel has been tested only with 2,2,1 configuration, so for
now we blindly create 2,2,1 topology when DSC is enabled
Co-developed-by: Abhinav Kumar
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
This add the bits in RM to enable the DSC blocks
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 56 +
drivers/gpu/drm/msm/disp/dpu1
Add a mode valid callback for dsi_mgr for checking mode being valid in
case of DSC. For DSC the height and width needs to be multiple of slice,
so we check that here
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi.h
Somehow documentation for num_dspp was missed, so add that
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/msm_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 10
drivers/gpu/drm/msm/dsi/dsi_host.c | 94 +-
2 files changed, 103 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 49b551ad1bff
On 28-03-22, 19:43, Dmitry Baryshkov wrote:
> On Mon, 28 Mar 2022 at 18:30, Krzysztof Kozlowski
> wrote:
> >
> > The DSI node is not a bus and the children do not have unit addresses.
> >
> > Reported-by: Vinod Koul
> > Signed-off-by: Krzysztof Kozlowski
&g
On 28-03-22, 13:21, Rob Herring wrote:
> On Mon, Mar 28, 2022 at 12:18 PM Krzysztof Kozlowski
> wrote:
> >
> > On 28/03/2022 19:16, Vinod Koul wrote:
> > > On 28-03-22, 19:43, Dmitry Baryshkov wrote:
> > >> On Mon, 28 Mar 2022 at 18:30, Krzysztof Kozlowski
:
- Rebase changes to the latest code base.
- Append rotation config variables with v2 and
remove unused variables.(Dmitry)
- Move pixel_ext setup separately from scaler3 config.(Dmitry)
- Add 270 degree rotation to supported rotation list.(Dmitry)
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod
Panels with higher refresh rate will need mdp clk above 300Mhz.
Select max frequency for mdp clock during bootup, dpu driver will
scale down the clock as per usecase when first update from the framework is
received.
Signed-off-by: Vinod Polimera
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2
Use atomic enable/disable for bridge callbacks to access certain
states like self-refresh.
This change avoids panel prepare/unprepare based on self-refresh
state.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Changes in V2:
- As per review
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 31 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 30 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
3 files changed, 57 insertions(+), 6 deletions
Use atomic variants for encoder callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Changes in v2:
- As per review suggestion by Dmitry.
---
drivers/gpu/drm/msm/disp/dpu1
*** BLURB HERE ***
Vinod Polimera (4):
drm/msm/dp: Add basic PSR support for eDP
drm/bridge: use atomic enable/disable for bridge callbacks
drm/msm/disp/dpu1: use atomic enable/disable callbacks for encoder
functions
drm/msm/disp/dpu1: add PSR support for eDP interface in dpu driver
Add support for basic panel self refresh (PSR) feature for eDP.
Add a new interface to set PSR state in the sink from DPU.
Program the eDP controller to issue PSR enter and exit SDP to
the sink.
Signed-off-by: Sankeerth Billakanti
Changes in v2:
- Use dp bridge to set psr entry/exit instead of
*** BLURB HERE ***
Vinod Polimera (2):
arm64/dts/qcom/sc7280: remove assigned-clock-rate property for mdp clk
drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table
arch/arm64/boot/dts/qcom/sc7280.dtsi| 9 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +++
2 files
use max clock during resume sequence from the opp table.
The clock will be scaled down when framework sends an update.
Fixes: 62fbdce91("arm64: dts: qcom: sc7280: add display dt nodes")
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +++
1 file
: add display dt nodes")
Signed-off-by: Vinod Polimera
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index baf1653..408cf6c 100644
--- a/arch/
icetree/bindings/mtd/nand-controller.yaml | 8 +++-
> .../bindings/mtd/rockchip,nand-controller.yaml| 3 +--
> .../devicetree/bindings/net/ti,cpsw-switch.yaml | 3 +--
> .../bindings/phy/phy-stm32-usbphyc.yaml | 3 +--
Acked-By: Vinod Koul
--
~Vinod
*** BLURB HERE ***
Vinod Polimera (3):
arm64/dts/qcom/sc7280: remove assigned-clock-rate property for mdp clk
arm64/dts/qcom/sc7180: remove assigned-clock-rate property for mdp clk
arm64/dts/qcom/sdm845: remove assigned-clock-rate property for mdp clk
arch/arm64/boot/dts/qcom/sc7180.dtsi
uency in opp
table"
Fixes: 62fbdce91("arm64: dts: qcom: sc7280: add display dt nodes")
Signed-off-by: Vinod Polimera
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch
c7180: add display dt nodes")
Signed-off-by: Vinod Polimera
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index e1c46b8..eaab746 100644
--- a/
dm845: Add dpu to sdm845 dts file")
Signed-off-by: Vinod Polimera
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0d6286d..80dc486 100644
er.kernel.org; robdcl...@gmail.com;
> diand...@chromium.org; quic_kalyant
> Subject: Re: [PATCH v2 2/2] drm/msm/disp/dpu1: set mdp clk to the
> maximum frequency in opp table
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and d
uency in opp
table"
Changes in v4:
- Add similar change for sm8250.(Dmitry)
Vinod Polimera (4):
arm64/dts/qcom/sc7280: remove assigned-clock-rate property for mdp clk
arm64/dts/qcom/sc7180: remove assigned-clock-rate property for mdp clk
arm64/dts/qcom/sdm845: remove assigned-clock-rat
c7180: add display dt nodes")
Signed-off-by: Vinod Polimera
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index e1c46b8..eaab746 100644
--- a/
m8250.dtsi: add display system nodes")
Signed-off-by: Vinod Polimera
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index fdaf303..2105eb7 100644
dm845: Add dpu to sdm845 dts file")
Signed-off-by: Vinod Polimera
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0d6286d..80dc486 100644
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