[PATCH 1/6] drm/i915: Add P010, P012, P016 plane control definitions

From: Juha-Pekka Heikkila Add needed plane control flag definitions for P010, P012 and P016 formats. Signed-off-by: Juha-Pekka Heikkila Signed-off-by: Swati Sharma Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/driver

[PATCH 2/6] drm/i915: Preparations for enabling P010, P012, P016 formats

From: Juha-Pekka Heikkila Preparations for enabling P010, P012 and P016 formats. These formats will extend NV12 for larger bit depths. Signed-off-by: Juha-Pekka Heikkila Signed-off-by: Swati Sharma Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +- drivers/

[PATCH 3/6] drm/i915: Enable P010, P012, P016 formats for primary and sprite planes

From: Juha-Pekka Heikkila Enabling of P010, P012 and P016 formats. These formats will extend NV12 for larger bit depths. Signed-off-by: Juha-Pekka Heikkila Signed-off-by: Swati Sharma Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_sprite.c | 28 ++-- 1

[PATCH 0/6] Enable P0xx (planar), Y2xx/Y4xx (packed) pixel formats

This patch series is for enabling P0xx, Y2xx and Y4xx pixel formats for intel's i915 driver. In this patch series, Juha Pekka's patch series Gen10+ P0xx formats https://patchwork.freedesktop.org/series/56053/ is combined with Swati's https://patchwork.freedesktop.org/series/55035/ for Gen11+ pixel

[PATCH 5/6] drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitions

Added needed plane control flag definitions for Y2xx and Y4xx (10, 12 and 16 bits) Signed-off-by: Swati Sharma Signed-off-by: Vidya Srinivas Reviewed-by: Juha-Pekka Heikkila Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ 1 file changed, 6 insertions(+) diff --

[PATCH 4/6] drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc

The following pixel formats are packed format that follows 4:2:2 chroma sampling. For memory represenation each component is allocated 16 bits each. Thus each pixel occupies 32bit. Y210: For each component, valid data occupies MSB 10 bits. LSB 6 bits are filled with zeroes. Y212: For e

[PATCH 6/6] drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planes

Signed-off-by: Swati Sharma Signed-off-by: Vidya Srinivas Reviewed-by: Juha-Pekka Heikkila Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_display.c | 30 ++ drivers/gpu/drm/i915/intel_sprite.c | 60 +++- 2 files changed, 89 insert