ems to me that the current code does not what atomic is asking for,
checking that is on my 2do...
I tested this patch individually, using modesetting driver. Things seem
to work as they did before.
Acked-by: Stefan Agner
But I guess to test the non-blocking commit, I would have to apply the
to true.
Use flat regmap cache and specify max register to be large
enouth to cover all registers available in LS1021a and Vybrids
register space.
Signed-off-by: Stefan Agner
Cc: Mark Brown
Cc: stable at vger.kernel.org
---
While regmap cache is used for suspend/resume only (which is
broken in
On 2016-05-26 02:11, Alexander Stein wrote:
> On Thursday 26 May 2016 08:23:42, Meng Yi wrote:
>> Hi Mark,
>>
>> > You've not specifically described the problem here - what are the
>> > endiannesses of both the CPU and the device you're talking to? What
>> > specifically is the endianess problem y
://lists.freedesktop.org/archives/dri-devel/2016-June/109625.html
Dave, Thierry: Could you have a look at patch 1? If that looks good
for you I will take it through my tree...
Changes since v1:
- Rebase ontop of drm-next + regmap cache fix
Stefan Agner (6):
drm/fb_cma_helper: add suspend helper
drm/fsl
Implement a suspend/resume helper for CMA users which calls
drm_fb_helper_set_suspend.
Suggested-by: Thierry Reding
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/drm_fb_cma_helper.c | 15 +++
include/drm/drm_fb_cma_helper.h | 1 +
2 files changed, 16 insertions(+)
diff
Store the number of registers per layer in soc_data. This is
more consistent with how the rest of SoC specific data are
handled.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 8 ++--
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 2 ++
drivers/gpu/drm/fsl-dcu
Move the initialization code for layers into a separate function
in the plane file. This allows to reuse the function on resume.
Also move it at the very beginning which may not matter but makes
logically much more sense.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu
Use clk_prepare_enable and clk_disable_unprepare helpers. This also
fixes a sequence issue in the enable path which lead to a warning
on resume.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff
Use the drm_atomic_helper_suspend() and drm_atomic_helper_resume()
helpers to implement subsystem-level suspend/resume. This replaces
the (non-functional) regmap cache based suspend resume functionality.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 40
-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index ca0f7d83..36df2eb 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b
On 2016-06-03 16:00, Daniel Vetter wrote:
> On Fri, Jun 03, 2016 at 03:43:19PM -0700, Stefan Agner wrote:
>> Using flat regmap cache instead of RB-tree to avoid the following
>> lockdep warning on driver load:
>> WARNING: CPU: 0 PID: 1 at kernel/locking/lockdep.c:2755
>>
since v1:
> - Invert polarity - driving pixel data on the falling edge and sampling
>it at the rising edge is the default.
> - Rename imx_drm_set_bus_format_pins to imx_drm_set_bus_config as now,
>additionally to bus format and pins, it also sets polarities.
Looks good
On 2016-06-06 19:16, Meng Yi wrote:
> Hi Stefan,
>
> Sorry for reply late, I was on PTO. And another PTO on June 9~11, 2016.UTC+8
>
>> >> static const struct regmap_config fsl_dcu_regmap_config = {
>> >> .reg_bits = 32,
>> >> .reg_stride = 4,
>> >> .val_bits = 32,
>> >> .cache_ty
ce492b3b8f99cf9d2f807ec22d8805c996a09503:
drm/fsl-dcu: use flat regmap cache (2016-06-08 15:12:01 -0700)
Stefan Agner (1):
drm/fsl-dcu: use flat regmap cache
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Hi Meng,
Some comments below.
On 2016-05-15 01:34, Meng Yi wrote:
> This driver add the basic functions for Encoder, and link the Encoder to
> appropriate DRM bridge.
> This driver is depend on sii9022 driver(drm_bridge approach),which is
> sent by Boris Brezillon to community but not merged.
> h
On 2016-06-11 18:55, Meng Yi wrote:
> Hi Stefan,
>
> Thanks for your comments, and some feedback below:
>
>> > +
>> > +#include
>> > +#include
>> > +#include
>> > +#include
>> > +#include
>> > +#include
>>
>> I think you don't use i2c here anymore, so this include (and probably a lot
>> oth
On 2016-06-16 21:02, Meng Yi wrote:
> The lable fail_connector should placed before fail_encoder since encoder was
> initialized before connector. which should also be called after
> connector initialization failed.
>
> Hi Stefan,
>
> What do you think?
The current error handling is wrong, I agr
Commit 7566e247672d ("drm/fsl-dcu: handle initialization errors properly")
introduced error handling during initialization, but with a wrong cleanup
order.
Replace the error handling with the generic cleanup function
drm_mode_config_cleanup.
Signed-off-by: Stefan Agner
---
drivers/g
On 2016-06-14 02:20, Meng Yi wrote:
> This patch creates another Encoder for HDMI port, and linking the Encoder
> to appropriate DRM bridge. And this Encoder using same CRTC with RGB-LCD.
> For RGB-LCD and HDMI using the same hardware connection to DCU, RGB-LCD
> panel should be unplugged when usin
On 2016-06-24 12:44, Anthony Felice wrote:
> Add driver for the Vybrid Tower CRTouch-based touchscreen. This is
> required for the touchscreen on the TWR-LCD-RGB to work on the Vybrid
> Tower platform.
>
> There is a known issue with this driver: rarely, SW1 on the TWR-LCD-RGB
> module needs to be
ock polarity changes which will be part of 4.7 work for
Tower? I could never actually test that since I don't have the display
here...
https://patchwork.kernel.org/patch/8874971/
This patch looks good to me:
Acked-by: Stefan Agner
--
Stefan
>
> Signed-off-by: Anthony Felice
> ---
:
drm/fsl-dcu: disable vblank events on CRTC disable (2016-06-18 18:34:31 -0700)
Stefan Agner (6):
drm/fb_cma_helper: add suspend helper
drm/fsl-dcu: store layer registers in soc_data
drm/fsl-dcu: move layer
Use "drm/fsl-dcu:" in the subject, that is what we commonly used.
On 2016-06-24 02:00, Meng Yi wrote:
> This patch rework the output code to add of_graph dt binding support
> for panel device and also keeps the backward compatibility
>
> Signed-off-by: Meng Yi
> ---
> drivers/gpu/drm/fsl-dcu/fs
On 2016-06-24 02:00, Meng Yi wrote:
> The current output code only supports connection to drm panels.
> Add codes to support drm bridge, to supports connection to
I sense to many s here.
Code in the C program code sense is typically an uncountable noun, hence
drop the s.
And "to support connecti
extensively written registers seem to be unassigned, it seems
that the write to those registers did not do any harm in practice.
Signed-off-by: Stefan Agner
---
This two patches apply cleanly on top of my earlier DCU fixes
patchset
ing used which has fast_io set to true.
The MMIO space of the DCU driver is reasonable condense, hence
using the much faster flat regmap cache is anyway the better
choice.
Signed-off-by: Stefan Agner
Cc: Mark Brown
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 20
drivers/
Hi Meng Yi,
As I wrote earlier
(http://www.spinics.net/lists/dri-devel/msg95703.html), my fixes
patchset contains a similar patch which also explicitly disable the
VBLANK interrupt. I think it is the better solution... See:
https://lkml.org/lkml/2015/11/18/951
I will soon prepare a git tree and p
2f1412a05
> Author: Stefan Agner
> Date: Sat Dec 19 21:52:58 2015 -0800
>
> kmstest: Use util_open()
>
> Use the new util_open() helper instead of open-coding the method for
> finding a usable device. While at it, make the command-line interface
> more co
d a pull request to Dave for the 4.6
merge window.
--
Stefan
>
> On Thu, Jan 7, 2016 at 2:02 PM, Stefan Agner wrote:
>> Promote myself as new maintainer of the Freescale DCU DRM driver.
>>
>> Signed-off-by: Stefan Agner
>> ---
>> This has been previously d
On 2016-01-26 13:18, Emil Velikov wrote:
> On 14 January 2016 at 08:23, Meng Yi wrote:
>>> >> switch (fb->pixel_format) {
>>> >> case DRM_FORMAT_RGB565:
>>> >> case DRM_FORMAT_RGB888:
>>> >> @@ -85,9 +88,6 @@ static void fsl_dcu_drm_plane_atomic_update(struct
>>> drm_plane
Hi Dave, Hi Thierry,
Not sure how to handle this patch: it contains a little change in
panel-simple.c. I think this should be in one patch, since it changes
the associated logic in the driver... Can I send that through my tree?
--
Stefan
On 2015-11-18 18:42, Stefan Agner wrote:
> The curr
On 2016-07-04 00:40, Peter Chen wrote:
> of_node_put needs to be called when the device node which is got
> from of_parse_phandle has finished using, but current code only
> calls it at error path, fix it by adding it at correct code path.
>
> Signed-off-by: Peter Chen
> ---
> drivers/gpu/drm/fs
On 2016-06-28 02:32, Meng Yi wrote:
> This patch rework the output code to add of_graph dt binding support
> for panel device and also keeps the backward compatibility
>
> Signed-off-by: Meng Yi
> ---
> Changes in V2:
> -fix some coding style issue
> -add fsl_dev->connector.panel check
> -use fsl
On 2016-06-29 01:17, Meng Yi wrote:
> dropped the old "fsl,panel" property, using the of_graph dt
> binding syntax
>
> Signed-off-by: Meng Yi
> ---
> Changes in V2:
> -drop the unit address of port
> ---
> Documentation/devicetree/bindings/display/fsl,dcu.txt | 9 +++--
> 1 file changed, 7 i
On 2016-06-29 01:17, Meng Yi wrote:
> add of_graph dt binding for panel, and "fsl,panel" property
Nit: "binding" typically describes the requirement, the specification
and hence is under Documentation/devicetree/bindings/.
What you add here is the dt nodes according to the bindings...
Hence I wo
Hi Meng,
This currently does not apply on top of drm-next, can you please rebase?
Some more comments below:
On 2016-07-14 03:54, Meng Yi wrote:
> This patch rework the output code to add of_graph dt binding support
> for panel device and also keeps the backward compatibility
>
> Signed-off-by:
On 2016-07-14 03:54, Meng Yi wrote:
> The current output code only supports connection to drm panels.
> Add code to support drm bridge, to support connections to
> external connectors.
>
> Signed-off-by: Meng Yi
> ---
> Changes since V1:
> -no change
> ---
> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_r
On 2016-07-14 23:53, Meng Yi wrote:
> This patch rework the output code to add of_graph dt binding support
> for panel device and also keeps the backward compatibility
>
> Signed-off-by: Meng Yi
Applied, with Rob's Ack from the earlier documentation only patch for
the Documentation part.
--
Ste
Hi Dave,
This adds drm bridge support for the NXP/Freescale DCU. The patchset
has been discussed on the mailing list since quite some time...
Plus there is a small fix provided by Peter.
--
Stefan
The following changes since commit f82c13722275b6aca3a956a82846465ec789b367:
Merge branch 'exyno
Hi Dave,
On 2016-11-28 18:55, Stefan Agner wrote:
> Hi Dave,
>
> Some fixes and cleanup, mainly around fbdev emulation. It also adds a
> new module parameter which allows to specify the color depth/bpp for
> the fbdev emulation (like the IMX DRM driver).
>
> There have be
On 2016-12-06 04:36, Marek Vasut wrote:
> On 12/06/2016 08:53 AM, Daniel Vetter wrote:
>> On Tue, Dec 06, 2016 at 11:08:06AM +1000, Dave Airlie wrote:
>>> On 2 December 2016 at 04:02, Marek Vasut wrote:
Hi,
as asked by Daniel, I collected the MXSFB DT Acks and the driver and
wr
to be high active by default
and only change if explicitly requested via bus_flags. With
that defaults are:
- Data enable: high active
- Pixel clock polarity: controller drives data on negative edge
Signed-off-by: Stefan Agner
---
Hi Marek,
I discovered this while testing on a i.MX 7 eLCDIF IP
3:59 -0800)
Fabio Estevam (2):
drm/fsl-dcu: Remove unneeded NULL check
drm/fsl-dcu: Propagate the real error code
Stefan Agner (4):
drm/fsl-dcu: unload driver before disabling clocks
drm/fsl-dcu: disable outputs before unload
On 2016-12-07 16:49, Marek Vasut wrote:
> On 12/08/2016 01:27 AM, Stefan Agner wrote:
>> The DRM subsystem specifies the pixel clock polarity from a
>> controllers perspective: DRM_BUS_FLAG_PIXDATA_NEGEDGE means
>> the controller drives the data on pixel clocks falling
On 2016-12-07 16:59, Stefan Agner wrote:
> On 2016-12-07 16:49, Marek Vasut wrote:
>> On 12/08/2016 01:27 AM, Stefan Agner wrote:
>>> The DRM subsystem specifies the pixel clock polarity from a
>>> controllers perspective: DRM_BUS_FLAG_PIXDATA_NEGEDGE means
>>&g
On 2016-12-07 18:37, Marek Vasut wrote:
> On 12/08/2016 02:26 AM, Stefan Agner wrote:
>> On 2016-12-07 16:59, Stefan Agner wrote:
>>> On 2016-12-07 16:49, Marek Vasut wrote:
>>>> On 12/08/2016 01:27 AM, Stefan Agner wrote:
>>>>> The DRM subsys
. Choose the
first available or fallback to 24 bit if none are available.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 28 +---
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 1 +
2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm
The display has a 18-Bit parallel LCD interface, require DE to be
active high and data driven by the controller on falling pixel
clock edge (display samples on rising edge).
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/panel/panel-simple.c | 4
1 file changed, 4 insertions(+)
diff
On 2016-12-08 15:33, Marek Vasut wrote:
> On 12/08/2016 11:52 PM, Stefan Agner wrote:
>> The LCD bus width does not need to align with the pixel format. The
>> LCDIF controller automatically converts between pixel formats and
>> bus width by padding or dropping LSBs.
>&g
with drm_put_dev. Call the unregister/unref parts
>> > separately, to make sure this driver works correct.
>> >
>> > v2: Rebase.
>> >
>> > Cc: Lucas Stach
>> > Cc: Stefan Agner
>> > Signed-off-by: Daniel Vetter
>>
>> Revi
On 2016-12-08 20:24, Marek Vasut wrote:
> On 12/09/2016 04:44 AM, Stefan Agner wrote:
>> On 2016-12-08 15:33, Marek Vasut wrote:
>>> On 12/08/2016 11:52 PM, Stefan Agner wrote:
>>>> The LCD bus width does not need to align with the pixel format. The
>>>&g
On 2016-12-08 15:38, Marek Vasut wrote:
> On 12/08/2016 09:46 PM, Stefan Agner wrote:
>> On 2016-12-07 18:37, Marek Vasut wrote:
>>> On 12/08/2016 02:26 AM, Stefan Agner wrote:
>>>> On 2016-12-07 16:59, Stefan Agner wrote:
>>>>> On 2016-12-07 16:49, Mar
. Choose the
first available or fallback to 24 bit if none are available.
Signed-off-by: Stefan Agner
---
Changes in v2:
- Use seperate function mxsfb_set_bus_fmt
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 33 +++--
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 1 +
2 files changed, 32
On 2016-12-14 00:04, Marek Vasut wrote:
> On 12/14/2016 01:01 AM, Stefan Agner wrote:
>> On 2016-12-08 15:38, Marek Vasut wrote:
>>> On 12/08/2016 09:46 PM, Stefan Agner wrote:
>>>> On 2016-12-07 18:37, Marek Vasut wrote:
>>>>> On 12/08/2016 02:26 AM, S
to be high active by default
and only change if explicitly requested via bus_flags. With
that defaults are:
- Data enable: high active
- Pixel clock polarity: controller drives data on negative edge
Signed-off-by: Stefan Agner
---
Changes since v1:
- Improved comments/fixed typo
drivers/gpu/drm
On 2016-12-13 23:52, Marek Vasut wrote:
> On 12/14/2016 02:02 AM, Stefan Agner wrote:
>> The LCD bus width does not need to align with the pixel format. The
>> LCDIF controller automatically converts between pixel formats and
>> bus width by padding or dropping LSBs.
>&g
. Choose the
first available or fallback to 24 bit if none are available.
Signed-off-by: Stefan Agner
---
Changes in v3:
- Use read-modify-write to update the LCDC_CTRL field
Changes in v2:
- Use seperate function mxsfb_set_bus_fmt
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 34
Hi Dongsheng,
On 2015-12-01 00:16, Dongsheng Wang wrote:
> From: Jianwei Wang
>
> For DCU support atmost 16 layers(on ls1021a) or 64 layers(on vf610),
> add (total_layer - 1) overlay planes.
>
> Signed-off-by: Jianwei Wang
> Signed-off-by: Yi Meng
> Signed-off-by: Wang Dongsheng
>
> diff --
[also added Jianwei Wang, since he is the current maintainer of this
driver]
On 2015-12-01 00:16, Dongsheng Wang wrote:
> From: Jianwei Wang
>
> Switch update interrupt mask bit with regmap_update_bits, and clear
> interrupt status by writing 1 to relevant bit before setting mask in
> fsl_dcu_dr
Hi Laurent,
On 2016-12-18 21:31, Laurent Pinchart wrote:
> Hi Stefan and Thierry,
>
> As the author and suggester of the other bus flags, could you please review
> this patch ?
It looks to me like an appropriate use case for the flag. One remark
below:
>
> On Saturday 19 Nov 2016 05:28:04 Lau
On 2016-12-20 14:21, Laurent Pinchart wrote:
> Hi Stefan,
>
> Thank you for the review.
>
> On Tuesday 20 Dec 2016 14:01:46 Stefan Agner wrote:
>> On 2016-12-18 21:31, Laurent Pinchart wrote:
>> > Hi Stefan and Thierry,
>> >
>> > As the author
On 2016-12-28 19:53, Gabriel Krisman Bertazi wrote:
> Fabio Estevam writes:
>
>> On Wed, Dec 28, 2016 at 4:38 PM, Gabriel Krisman Bertazi
>> wrote:
>>
>>> This leaks tcon if clk_prepare_enable fails.
>>
>> No, it does not as tcon is allocated via devm_kzalloc().
>
> Agreed. But I think devm_kz
Hi Meng Yi,
I plan to review the patchset too, but did not come around yet.
The forth patch conflicts with my changes in the DRM DCU driver. Since
it will likely go through my tree, please base v2 ontop of my DCU
branch:
http://git.agner.ch/gitweb/?p=linux-drm-fsl-dcu.git;a=summary
--
Stefan
On
On 2016-01-20 18:50, Stefan Agner wrote:
> Using flat regmap cache instead of RB-tree to avoid the following
> lockdep warning on driver load:
> [0.697285] WARNING: CPU: 0 PID: 1 at kernel/locking/lockdep.c:2755
> lockdep_trace_alloc+0x15c/0x160()
> [0.697449] DEBU
extensively written registers seem to be unassigned, it seems
that the write to those registers did not do any harm in practice.
Signed-off-by: Stefan Agner
---
This two patches apply cleanly on top of my earlier DCU fixes
patchset
ing used which has fast_io set to true.
The MMIO space of the DCU driver is reasonable condense, hence
using the much faster flat regmap cache is anyway the better
choice.
Signed-off-by: Stefan Agner
Cc: Mark Brown
---
Changes since v1:
- Do not move drm_dev_alloc
drivers/gpu/drm/fsl-
On 2016-02-03 06:00, Thierry Reding wrote:
> On Wed, Jan 27, 2016 at 06:46:50PM -0800, Stefan Agner wrote:
> [...]
>> > diff --git a/drivers/gpu/drm/panel/panel-simple.c
>> > b/drivers/gpu/drm/panel/panel-simple.c
>> > index f97b73e..fa68b56 100644
>> >
On 2016-02-03 06:04, Thierry Reding wrote:
> On Wed, Jan 27, 2016 at 06:46:50PM -0800, Stefan Agner wrote:
> [...]
>> On 2015-11-18 18:42, Stefan Agner wrote:
> [...]
>> > diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
> [...]
>>
On 2016-02-03 15:18, Stefan Agner wrote:
> On 2016-02-03 06:00, Thierry Reding wrote:
>> On Wed, Jan 27, 2016 at 06:46:50PM -0800, Stefan Agner wrote:
>> [...]
>>> > diff --git a/drivers/gpu/drm/panel/panel-simple.c
>>> > b/drivers/gpu/drm/panel/panel-simpl
s_flags stored in struct drm_display_info.
--
Stefan
Changes since v1:
- Introduce bus_flags to convey the pixel clock polarity from
panel-simple.c to the driver.
Stefan Agner (3):
drm/fsl-dcu: use mode flags for hsync/vsync polarity
drm: introduce bus_flags in drm_display_info
dr
flags are specified):
- VSYNC signal not inverted (active HIGH)
- HSYNC signal not inverted (active HIGH)
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 11 ---
drivers/gpu/drm/panel/panel-simple.c | 1 +
2 files changed, 9 insertions(+), 3 deletion
Introduce bus_flags to specify display bus properties like signal
polarities. This is useful for parallel display buses, e.g. to
specify the pixel clock or data enable polarity.
Suggested-by: Thierry Reding
Signed-off-by: Stefan Agner
---
include/drm/drm_crtc.h | 9 +
1 file changed, 9
ned-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 5 +
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 4 ++--
drivers/gpu/drm/panel/panel-simple.c | 5 -
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
b/drive
On 2016-02-02 17:06, Stefan Agner wrote:
> Using flat regmap cache instead of RB-tree to avoid the following
> lockdep warning on driver load:
> [0.697285] WARNING: CPU: 0 PID: 1 at kernel/locking/lockdep.c:2755
> lockdep_trace_alloc+0x15c/0x160()
> [0.697449] DEBU
Hi Meng,
I did not come around to have a proper look at this, but some stuff to
start with below:
On 2016-02-15 17:52, Meng Yi wrote:
> DCU is the shortcut of 'display controller unit', some HDMI transmitter
> attached to DCU, such as sii9022a, and this driver add the relavent
> functions to DRM
Simplified TCON driver by removing suspend/resume
capabilities (encoder disable/enable makes sure that
TCON bypass gets disabled/reenabled on suspend)
- Use common clock framework to create a divider clock
which represents the DCU internal pixel clock divider
Stefan Agner (9):
ARM: imx: clk-
parent clock of VF610_CLK_DCUx to be the bus
clock (ipg_bus).
Since the clock has not been used far, there are no further changes
needed.
Signed-off-by: Stefan Agner
---
drivers/clk/imx/clk-vf610.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-vf610
Add the ipg (bus) clock for the TCON modules (Timing Controller). This
module is required by the new DCU DRM driver, since the display signals
pass through TCON.
Signed-off-by: Stefan Agner
---
drivers/clk/imx/clk-vf610.c | 3 +++
include/dt-bindings/clock/vf610-clock.h | 4 +++-
2
Fix error handling during probe by reordering initialization and
adding a error path which disables clock again. Also disable the
clock on remove.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 44 +++
1 file changed, 21 insertions(+), 23
The Vybrid DCU variant has two independent clock inputs, one
for the registers (IPG bus clock) and one for the pixel clock.
Support this distinction in the DCU DRM driver while staying
backward compatible for old device trees.
Signed-off-by: Stefan Agner
---
Documentation/devicetree/bindings
it also allows to see
the actual pixel clock in the sysfs clock summary.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 7 ++-
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 26 ++
2 files changed, 24 insertions(+), 9 deletions(-)
diff
iming signals for raw TFT panels
or operate in a bypass mode which leaves all signals unaltered.
The driver currently only supports the bypass mode.
Acked-by: Rob Herring
Signed-off-by: Stefan Agner
---
.../devicetree/bindings/display/fsl,dcu.txt| 4 +
.../devicetree/bindings/displa
Add the dcu and tcon nodes to enable the Display Controller Unit
and Timing Controller in Vybrid's SoC level device-tree file.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/vfxxx.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/vfxxx.d
Enable dcu node which is used by the DCU DRM driver. Assign the 5.7"
EDT panel with VGA resolution which Toradex sells often with the
evaluation board.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/vf-colibri-eval-v3.dtsi | 16 +++
arch/arm/boot/dts/vf-colibri.dtsi
The DCU IP has distinct clock inputs for register access and the
pixel clocks, at least in some implementations. LS1021a seems to
use the same clock, therefore specify the same clock for "dcu"
and "pix".
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/ls1021a.dtsi | 5 +++-
On 2016-04-11 18:38, Shawn Guo wrote:
> On Mon, Apr 04, 2016 at 10:28:33PM -0700, Stefan Agner wrote:
>> Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy
>> mixes the bus clock with the display controllers pixel clock. Tests
>> have shown that the
nts welcome...
Stefan Agner (6):
drm/fsl-dcu: detach panel on destroy
drm/fsl-dcu: handle missing panel gracefully
drm/fsl-dcu: use variable name dev for struct drm_device
drm/fsl-dcu: deallocate fbdev CMA on unload
drm/fsl-dcu: disable output polling on driver unload
drm/fsl-dcu: implem
Disable the earlier attached panel on connector destroy.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
index f586f1e..a07886f
If the device tree property fsl,panel is missing, drm_panel_attach
is called with a NULL pointer as first argument. Having a panel is
basically mandatory since RGB is the only supported connector.
Check if a panel node has been found, return -ENODEV and cleanup
otherwise.
Signed-off-by: Stefan
Disabling output polling before unloading the driver.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 182578d..f9227b7
The driver uses different variable names for struct drm_device
across functions which is confusing. Stick to the more common
variable name dev. While at it, remove unnecessary if statement
in error handling.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 29
Free fbdev CMA using drm_fbdev_cma_fini on unload. This fixes
a warning when unloading the driver:
WARNING: CPU: 0 PID: 164 at drivers/gpu/drm/drm_crtc.c:5930
drm_mode_config_cleanup+0x204/0x208
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 9 +
1 file
Use CMA helper drm_fbdev_cma_restore_mode to restore fbdev mode
in process which uses drm/kms dies.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
b/drivers/gpu/drm
s_flags to convey the pixel clock polarity from
panel-simple.c to the driver.
Stefan Agner (2):
drm: introduce bus_flags in drm_display_info
drm/fsl-dcu: use bus_flags for pixel clock polarity
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 5 +
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_
ned-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 5 +
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 4 ++--
drivers/gpu/drm/panel/panel-simple.c | 3 ++-
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
b/drive
Introduce bus_flags to specify display bus properties like signal
polarities. This is useful for parallel display buses, e.g. to
specify the pixel clock or data enable polarity.
Suggested-by: Thierry Reding
Acked-by: Philipp Zabel
Acked-by: Manfred Schlaegl
Signed-off-by: Stefan Agner
obsoletes this patch:
https://lkml.org/lkml/2016/3/24/281
Stefan Agner (6):
drm/fb_cma_helper: add suspend helper
drm/fsl-dcu: store layer registers in soc_data
drm/fsl-dcu: move layer initialization to plane file
drm/fsl-dcu: use clk helpers
drm/fsl-dcu: implement suspend/resume using
Move the initialization code for layers into a separate function
in the plane file. This allows to reuse the function on resume.
Also move it at the very beginning which may not matter but makes
logically much more sense.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu
Implement a suspend/resume helper for CMA users which calls
drm_fb_helper_set_suspend.
Suggested-by: Thierry Reding
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/drm_fb_cma_helper.c | 15 +++
include/drm/drm_fb_cma_helper.h | 1 +
2 files changed, 16 insertions(+)
diff
Store the number of registers per layer in soc_data. This is
more consistent with how the rest of SoC specific data are
handled.
Signed-off-by: Stefan Agner
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 8 ++--
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 2 ++
drivers/gpu/drm/fsl-dcu
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