Add the compatible because there are different definitions for cmdq
register bit control in mt8188.
Signed-off-by: Shuijing Li
Signed-off-by: Jitao Shi
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
drivers/gpu/drm/mediatek/mtk_dsi.c | 8
2 files
packets.
Base on the branch of linus/master v6.4.
Shuijing Li (3):
dt-bindings: display: mediatek: dsi: Add compatible for MediaTek
MT8188
drm/mediatek: Add mt8188 dsi compatible to mtk_dsi.c
drm/mediatek: dsi: Add dsi cmdq_ctl to send panel initial code
.../bindings/display/mediatek
Add dt-binding documentation of dsi for MediaTek MT8188 SoC.
Signed-off-by: Shuijing Li
Signed-off-by: Jitao Shi
Acked-by: Krzysztof Kozlowski
Reviewed-by: Matthias Brugger
---
.../devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
For mt8188, add dsi cmdq reg control to send long packets to panel
initialization.
Signed-off-by: Shuijing Li
Signed-off-by: Jitao Shi
---
Changes in v2:
use mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL); directly,
per suggestion from the previous thread:
https
For "boe,tv105wum-nw0" this special panel, it is stipulated in
the panel spec that MIPI needs to keep the LP11 state before
the lcm_reset pin is pulled high.
Signed-off-by: Shuijing Li
Signed-off-by: Xinlei Lee
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/panel
Reduce the delay after LCM reset by removing an extra delay in the
initialization commands array. The required delay of at least 6ms after
reset is guaranteed by boe_panel_prepare().
Signed-off-by: Shuijing Li
Signed-off-by: Xinlei Lee
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu
. Remove the applied patch.
2. Change the commit title and the description.
Change since v1:
1. Added fine-tuning panel power sequence modification.
Shuijing Li (2):
drm/panel: boe-tv101wum-nl6: Remove extra delay
drm/panel: boe-tv101wum-nl6: Fine tune the panel power sequence
drivers/gpu
to the difference of HW, different dividers need to be set.
Base on the branch of linus/master v6.4.
Shuijing Li (3):
dt-bindings: display: mediatek: dp: Add compatible for MediaTek MT8188
drm/mediatek: dp: Add the audio control to mtk_dp_data struct
drm/mediatek: dp: Add the audio divider
Add dt-binding documentation of dp-tx for MediaTek MT8188 SoC.
Signed-off-by: Shuijing Li
Signed-off-by: Jitao Shi
Reviewed-by: AngeloGioacchino Del Regno
Acked-by: Krzysztof Kozlowski
---
Changes in v2:
add a mediatek,mt8188-edp-tx compatible per suggestion from the previous thread:
https
Due to the difference of HW, different dividers need to be set.
Signed-off-by: Shuijing Li
Signed-off-by: Jitao Shi
---
Changes in v3:
Separate these two things into two different patches.
per suggestion from the previous thread:
https://lore.kernel.org/lkml
The audio packet arrangement function is to only arrange audio.
packets into the Hblanking area. In order to align with the HW
default setting of mt8195, this function needs to be turned off.
Signed-off-by: Shuijing Li
Signed-off-by: Jitao Shi
---
Changes in v3:
Separate these two things into
to the difference of HW, different dividers need to be set.
Base on the branch of linus/master v6.4.
Shuijing Li (3):
dt-bindings: display: mediatek: dp: Add compatible for MediaTek MT8188
drm/mediatek: dp: Add the audio packet flag to mtk_dp_data struct
drm/mediatek: dp: Add the audio
Due to the difference of HW, different dividers need to be set.
Signed-off-by: Shuijing Li
Signed-off-by: Jitao Shi
---
Changes in v4:
list all configuration for MT8188 and MT8195.
per suggestion from the previous thread:
https://lore.kernel.org/all/a9d1b9b7ef4780f51574d0bbbe28f6dd109a6ab8.ca
Add dt-binding documentation of dp-tx for MediaTek MT8188 SoC.
Signed-off-by: Shuijing Li
Signed-off-by: Jitao Shi
Reviewed-by: AngeloGioacchino Del Regno
Acked-by: Krzysztof Kozlowski
---
Changes in v2:
add a mediatek,mt8188-edp-tx compatible per suggestion from the previous thread:
https
The audio packet arrangement function is to only arrange audio.
packets into the Hblanking area. In order to align with the HW
default setting of mt8195, this function needs to be turned off.
Signed-off-by: Shuijing Li
Signed-off-by: Jitao Shi
---
Changes in v4:
drop mt8188_edp_data and remove
Add dt-binding documentation of dp-tx for MediaTek MT8188 SoC.
Signed-off-by: Shuijing Li
Signed-off-by: Jitao Shi
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: CK Hu
Acked-by: Krzysztof Kozlowski
---
Changes in v2:
add a mediatek,mt8188-edp-tx compatible per suggestion from the
to the difference of HW, different dividers need to be set.
Base on the branch of linus/master v6.4.
Shuijing Li (4):
dt-bindings: display: mediatek: dp: Add compatible for MediaTek MT8188
drm/mediatek: dp: Add the audio packet flag to mtk_dp_data struct
drm/mediatek: dp: Add the audio
Add mtk_dp_audio_sample_arrange_disable function for MT8188.
Signed-off-by: Shuijing Li
---
Changes in v5:
Separate mt8188 related code into mtk_dp_data structure and mt8188 dp/edp
function
per suggestion from the previous thread:
https://lore.kernel.org/lkml
The audio packet arrangement function is to only arrange audio
packets into the Hblanking area. In order to align with the HW
default setting of mt8195, this function needs to be turned off.
Signed-off-by: Shuijing Li
---
Changes in v5:
Separate mt8188 related code into mtk_dp_data structure and
Due to the difference of HW, different dividers need to be set.
Signed-off-by: Shuijing Li
---
Changes in v4:
list all configuration for MT8188 and MT8195.
per suggestion from the previous thread:
https://lore.kernel.org/all/a9d1b9b7ef4780f51574d0bbbe28f6dd109a6ab8.ca...@mediatek.com/
Changes in
Add support MT8188 dp/edp function
Signed-off-by: Shuijing Li
---
Changes in v6:
Move audio function to patch [2/4].
per suggestion from the previous thread:
https://lore.kernel.org/all/1d41747060c613ca0ae8e3b6395cc33bfa4d9056.ca...@mediatek.com/
Changes in v5:
Separate mt8188 related code into
Due to the difference of HW, different dividers need to be set.
Signed-off-by: Shuijing Li
---
Changes in v6:
Move MT8188 defintion to patch[4/4].
per suggestion from the previous thread:
https://lore.kernel.org/all/60ba1ab40fc943f1abf3e78b0b32223be402302c.ca...@mediatek.com/
Changes in v4:
list
to the difference of HW, different dividers need to be set.
Base on the branch of linus/master v6.4.
Shuijing Li (4):
dt-bindings: display: mediatek: dp: Add compatible for MediaTek MT8188
drm/mediatek: dp: Add the audio packet flag to mtk_dp_data struct
drm/mediatek: dp: Add the audio
The audio packet arrangement function is to only arrange audio
packets into the Hblanking area. In order to align with the HW
default setting of mt8195, this function needs to be turned off.
Signed-off-by: Shuijing Li
---
Changes in v6:
Move mt8188 related code to another patch
per suggestion
Add dt-binding documentation of dp-tx for MediaTek MT8188 SoC.
Signed-off-by: Shuijing Li
Signed-off-by: Jitao Shi
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: CK Hu
Acked-by: Krzysztof Kozlowski
---
Changes in v2:
add a mediatek,mt8188-edp-tx compatible per suggestion from the
Support IGT (Intel GPU Tools) in Mediatek DisplayPort driver
Signed-off-by: Shuijing Li
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 7d5250351193
: Shuijing Li
---
Changes in v2:
Correct descriptions of title and commit message.
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 7d5250351193..a494e04f0ddf
.
Signed-off-by: Shuijing Li
Signed-off-by: Jitao Shi
---
Changes in v2:
- change the variables' name to be more descriptive
- add a comment that describes the function of mtk_dp_audio_sample_arrange
- reduce indentation by doing the inverse check
- add a definition of some bits
- add suppor
to the difference of HW, different dividers need to be set.
Base on the branch of linus/master v6.4.
Shuijing Li (2):
dt-bindings: display: mediatek: dp: Add compatible for MediaTek MT8188
drm/mediatek: dp: Add the audio control to mtk_dp_data struct
.../display/mediatek/mediatek,dp.yaml
Add dt-binding documentation of dp-tx for MediaTek MT8188 SoC.
Signed-off-by: Shuijing Li
Signed-off-by: Jitao Shi
---
Changes in v2:
add a mediatek,mt8188-edp-tx compatible per suggestion from the previous thread:
https://lore.kernel.org/lkml/c4a4a900-c80d-b110-f10e-7fa2dae8b...@collabora.com
P^^RGB^^HFP^^HSA+HBP^^RGB^^HFP^
Per Line LP:
|<---One Active Frame--->|
--__--__--____
^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^^HSA+HBP^^RGB^
Signed-off-by: Shuijing Li
---
Changes in v8:
Directly writ
-off-by: Shuijing Li
---
Changes in v3:
reorder patch 2/3 and 3/3, and describe more about why mt8188 need this
patch,
per suggestion from the previous thread:
https://lore.kernel.org/lkml/411ddbf95e2c2298b84899065691d478069ec273.ca...@mediatek.com/
Changes in v2:
use mtk_dsi_mask(dsi
packets.
Base on the branch of linus/master v6.5.
Shuijing Li (3):
dt-bindings: display: mediatek: dsi: Add compatible for MediaTek
MT8188
drm/mediatek: dsi: Add dsi cmdq_ctl to send panel initial code
drm/mediatek: Add mt8188 dsi compatible to mtk_dsi.c
.../bindings/display/mediatek
Add the compatible because there are different definitions for cmdq
register bit control in mt8188.
Signed-off-by: Shuijing Li
---
Changes in v3:
reorder patch 2/3 and 3/3,
per suggestion from the previous thread:
https://lore.kernel.org/lkml/338122485db025f6bfb8be550d426ca11698497c.ca
Add dt-binding documentation of dsi for MediaTek MT8188 SoC.
Signed-off-by: Shuijing Li
Signed-off-by: Jitao Shi
Acked-by: Krzysztof Kozlowski
Reviewed-by: Matthias Brugger
---
.../devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
packets.
Base on the branch of linus/master v6.5.
Shuijing Li (3):
dt-bindings: display: mediatek: dsi: Add compatible for MediaTek
MT8188
drm/mediatek: dsi: Add dsi cmdq_ctl to send panel initial code
drm/mediatek: Add mt8188 dsi compatible to mtk_dsi.c
.../bindings/display/mediatek
Add the compatible because there are different definitions for cmdq
register bit control in mt8188.
Signed-off-by: Shuijing Li
Reviewed-by: AngeloGioacchino Del Regno
---
Changes in v3:
reorder patch 2/3 and 3/3,
per suggestion from the previous thread:
https://lore.kernel.org/lkml
-off-by: Shuijing Li
Reviewed-by: AngeloGioacchino Del Regno
---
Changes in v4:
Add a comment per suggestion from the previous thread:
https://lore.kernel.org/all/14e03873-3723-8293-0190-445a71828...@collabora.com/
Changes in v3:
reorder patch 2/3 and 3/3, and describe more about why mt8188 need
Add dt-binding documentation of dsi for MediaTek MT8188 SoC.
Signed-off-by: Shuijing Li
Signed-off-by: Jitao Shi
Acked-by: Krzysztof Kozlowski
Reviewed-by: Matthias Brugger
Reviewed-by: AngeloGioacchino Del Regno
---
.../devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 1 +
1
P^^RGB^^HFP^^HSA+HBP^^RGB^^HFP^
Per Line LP:
|<---One Active Frame--->|
--__--__--____
^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^^HSA+HBP^^RGB^
Signed-off-by: Shuijing Li
---
drivers/gpu/drm/mediatek/mtk
This patch correct calculation formula of PHY timing.
Make actual phy timing more accurate.
Signed-off-by: Shuijing Li
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 33 +++---
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
P^^RGB^^HFP^^HSA+HBP^^RGB^^HFP^
Per Line LP:
|<---One Active Frame--->|
--__--__--____
^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^^HSA+HBP^^RGB^
Signed-off-by: Shuijing Li
---
Changes in v3:
Use function i
P^^RGB^^HFP^^HSA+HBP^^RGB^^HFP^
Per Line LP:
|<---One Active Frame--->|
--__--__--____
^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^^HSA+HBP^^RGB^
Signed-off-by: Shuijing Li
---
Changes in v4:
Drop the cod
P^^RGB^^HFP^^HSA+HBP^^RGB^^HFP^
Per Line LP:
|<---One Active Frame--->|
--__--__--____
^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^^HSA+HBP^^RGB^
Signed-off-by: Shuijing Li
---
Changes in v5:
Fix code style i
P^^RGB^^HFP^^HSA+HBP^^RGB^^HFP^
Per Line LP:
|<---One Active Frame--->|
--__--__--____
^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^^HSA+HBP^^RGB^
Signed-off-by: Shuijing Li
---
Changes in v6:
Simplify
P^^RGB^^HFP^^HSA+HBP^^RGB^^HFP^
Per Line LP:
|<---One Active Frame--->|
--__--__--____
^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^^HSA+HBP^^RGB^
Signed-off-by: Shuijing Li
---
Changes in v7:
Fix code style
This patch correct calculation formula of PHY timing.
The spec define HS-PREPARE should be from 40ns+4*UI(44ns) to
85ns+6*UI(91ns). But current duration is 88ns and is near the boundary.
So this patch make the duration to 64ns so it is near the safe range.
Signed-off-by: Shuijing Li
---
Changes
P^^RGB^^HFP^^HSA+HBP^^RGB^^HFP^
Per Line LP:
|<---One Active Frame--->|
--__--__--____
^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^^HSA+HBP^^RGB^
Signed-off-by: Shuijing Li
---
Changes in v2:
Use bitfield ma
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