prot_writecombine() called for buffers,
which need store operations being combined. In case if particular MIPS
chip doesn't support the UCA attribute, the mapping will fall back to
noncached.
Cc: Ralf Baechle
Cc: Paul Burton
Cc: James Hogan
Signed-off-by: Vadim V. Vlasov
Signed-off-by
Hello folks,
Any updates of this patch status? It has been here for about two months.
Regards,
-Sergey
On Tue, Apr 23, 2019 at 03:31:22PM +0300, Serge Semin wrote:
> Since commit 4b050ba7a66c ("MIPS: pgtable.h: Implement the
> pgprot_writecombine function for MIPS") and com
Hello Sean,
On Tue, Jun 18, 2019 at 03:52:04PM -0400, Sean Paul wrote:
> On Mon, Jun 17, 2019 at 04:47:30PM +0300, Serge Semin wrote:
> > Hello folks,
> >
> > Any updates of this patch status? It has been here for about two months.
> >
>
> Sorry for the mix
On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> From: Conor Dooley
>
> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> this.
>
> Signed-off-by: Conor Dooley
> ---
> .../bindings/spi/snps
Hi Geert
On Tue, Jun 21, 2022 at 09:03:25AM +0200, Geert Uytterhoeven wrote:
> Hi Serge,
>
> On Mon, Jun 20, 2022 at 10:56 PM Serge Semin wrote:
> > On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> > > From: Conor Dooley
> > >
[...]
> &
On Tue, Jun 21, 2022 at 04:06:21PM +, conor.doo...@microchip.com wrote:
> On 21/06/2022 00:17, Damien Le Moal wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > On 6/21/22 07:49, Conor Dooley wrote:
> >>
> ---8<---
>
> h
On Mon, Jun 27, 2022 at 08:39:52PM +0100, Conor Dooley wrote:
> From: Conor Dooley
>
> Most users of dw-apb-ssi use spi-{r,t}x-bus-width of 1, however the
> Canaan k210 is wired up for a width of 4.
> Quoting Serge:
> The modern DW APB SSI controllers of v.4.* and newer also support the
> enhance
On Mon, Jun 27, 2022 at 08:39:54PM +0100, Conor Dooley wrote:
> From: Conor Dooley
>
> The Canaan k210 apparently has a Sysnopsys Designware timer but
> according to the documentation & devicetree it has 2 interrupts rather
> than the standard one. Add a custom compatible that supports the 2
> in
On Mon, Jun 27, 2022 at 08:39:53PM +0100, Conor Dooley wrote:
> From: Conor Dooley
>
> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
> controller, but according to the documentation & devicetree it has 6
> interrupts rather than the standard one. Add a custom compatible that
> sup
On Tue, Jun 28, 2022 at 09:08:32AM +0200, Geert Uytterhoeven wrote:
> Hi Conor,
>
> On Tue, Jun 28, 2022 at 8:30 AM wrote:
> > On 28/06/2022 00:29, Rob Herring wrote:
> > > EXTERNAL EMAIL: Do not click links or open attachments unless you know
> > > the content is safe
> > >
> > > On Sat, Jun 18
Hi Rob,
On Mon, Jun 27, 2022 at 05:30:25PM -0600, Rob Herring wrote:
> On Sat, Jun 18, 2022 at 01:30:27PM +0100, Conor Dooley wrote:
> > From: Conor Dooley
> >
> > The Canaan k210 apparently has a Sysnopsys Designware timer but
> > according to the documentation & devicetree it has 2 interrupts
r also support the
> enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core
> version is auto-detected at run-time there is no way to create a
> DT-schema correctly constraining the Rx/Tx SPI bus widths.
> /endquote
>
> As such, drop the restriction on only supporting a bus w
schema: Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
>
> Split the timer nodes in two, so that the second timer in the IP block
> can actually be accessed & in the process solve the dtbs_check warning.
Reviewed-by: Serge Semin
Just to note. IMO the DW APB Timer dr
ma_apb_regs
>
>interrupts:
> -maxItems: 1
> +description: per channel interrupts
Description is inaccurate. It's either combined or per-channel IRQs.
Other than that:
Reviewed-by: Serge Semin
-Sergey
> +minItems: 1
> +maxItems: 8
>
>clocks:
> items:
> --
> 2.36.1
>
_device *spi,
> bool enable)
> struct dw_spi *dws = spi_master_get_devdata(spi->master);
> struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio,
> dws);
> struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
> - u8 cs = spi->chip_select;
> + u8 cs = spi_get_chipselect(spi, 0);
>
> if (!enable) {
> /* CS override drive enable */
For the DW SSI part:
Reviewed-by: Serge Semin
-Serge(y)
[nip]
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