From: Rob Clark
Userspace is expecting that a single thread doing rendering against
multiple contexts does not need additional synchronization between those
contexts beyond ensuring work is flushed to the kernel in the correct
order. But if we have a sched-entity per-context, and are not using
From: Rob Clark
msm_file_private is more gpu related, and in the next commit it will
need access to other GPU specific #defines. While we're at it, add
some comments.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.h | 44 --
drivers/gpu/drm/msm/msm_
From: Rob Clark
Some userspace apps make assumptions that rendering against multiple
contexts within the same process (from the same thread, with appropriate
MakeCurrent() calls) provides sufficient synchronization without any
external synchronization (ie. glFenceSync()/glWaitSync()). Since a
On Fri, Oct 1, 2021 at 10:28 AM Dmitry Baryshkov
wrote:
>
> On 21/09/2021 01:57, Rob Clark wrote:
> > From: Rob Clark
> >
> > For now, since we have a mix of bridges which support this flag, which
> > which do *not* support this flag, or work both ways, try it once
On Fri, Oct 1, 2021 at 10:39 AM Dmitry Baryshkov
wrote:
>
> On 27/09/2021 21:03, Rob Clark wrote:
> > From: Rob Clark
> >
> > I've seen some crashes in our crash reporting that *look* like multiple
> > threads stomping on each other while communicating with GMU
From: Rob Clark
I've seen some crashes in our crash reporting that *look* like multiple
threads stomping on each other while communicating with GMU. So wrap
all those paths in a lock.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6
drivers/gpu/drm/msm/a
From: Rob Clark
This series extends io-pgtable-arm with a method to retrieve the page
table entries traversed in the process of address translation, and then
beefs up drm/msm gpu devcore dump to include this (and additional info)
in the devcore dump.
The motivation is tracking down an obscure
From: Rob Clark
Add an io-pgtable method to retrieve the raw PTEs that would be
traversed for a given iova access.
Signed-off-by: Rob Clark
---
drivers/iommu/io-pgtable-arm.c | 40 +++---
include/linux/io-pgtable.h | 9
2 files changed, 41 insertions
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 25 +
drivers/gpu/drm/msm/msm_gpu.h | 2 +-
3 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu
From: Rob Clark
In the case of iova fault triggered devcore dumps, include additional
debug information based on what we think is the current page tables,
including the TTBR0 value (which should match what we have in
adreno_smmu_fault_info unless things have gone horribly wrong), and
the
+ dri-devel, sorry hit 'send' too quickly
On Tue, Oct 5, 2021 at 3:45 PM Rob Clark wrote:
>
> Hi Dave & Daniel,
>
> A few fixes for v5.15:
>
> * Fix a new crash on dev file close if the dev file was opened when
> GPU is not loaded (such as missing
From: Rob Clark
For newer devices which deprecate gpu-id and do matching based on
chip-id, we need this information in cmdstream dumps so that the
decoding tools know how to decode them.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_rd.c | 4
1 file changed, 4 insertions(+)
diff
On Mon, Jan 17, 2022 at 6:38 AM Akhil P Oommen wrote:
>
> On 1/13/2022 12:43 PM, Dmitry Baryshkov wrote:
> > On Thu, 13 Jan 2022 at 00:19, Rob Clark wrote:
> >> On Tue, Jan 11, 2022 at 1:31 PM Akhil P Oommen
> >> wrote:
> >>> Expose speedbin t
On Wed, Jan 19, 2022 at 7:09 AM Daniel Vetter wrote:
>
> On Thu, Jan 06, 2022 at 04:55:35PM +, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > Proposal to standardise the fdinfo text format as optionally output by DRM
> > drivers.
> >
> > Idea is that a simple but, well defined, spec w
heck in dpu_setup_dspp_pcc
drm/msm/dsi: invalid parameter check in msm_dsi_phy_enable
Miaoqian Lin (2):
drm/msm/dsi: Fix missing put_device() call in dsi_get_phy
drm/msm/hdmi: Fix missing put_device() call in msm_hdmi_get_phy
Rob Clark (3):
drm/msm/a6xx: Add missing suspend_c
From: Rob Clark
Currently, for GL_EXT_robustness userspace uses the global and per-
submitqueue fault counters to determine GUILTY_CONTEXT_RESET_EXT vs
INNOCENT_CONTEXT_RESET_EXT. But that is a bit overly paranoid, in
that a fault in a different process's context (when it has it's ow
From: Rob Clark
Prep work for next patch.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ++-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 ++-
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
drivers/gpu/drm/msm/msm_gpu.h | 3 ++-
drivers/gpu/drm/msm
From: Rob Clark
Add a param so that userspace can query the fault count for faults that
might effect them (ie. any context sharing the same address space).
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++
drivers/gpu/drm/msm/msm_drv.c | 1 +
drivers/gpu
From: Rob Clark
Currently, for GL_EXT_robustness userspace uses the global and per-
submitqueue fault counters to determine GUILTY_CONTEXT_RESET_EXT vs
INNOCENT_CONTEXT_RESET_EXT. But that is a bit overly paranoid, in
that a fault in a different process's context (when it has it's ow
From: Rob Clark
Prep work for next patch.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ++-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 ++-
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
drivers/gpu/drm/msm/msm_gpu.h | 3 ++-
drivers/gpu/drm/msm
From: Rob Clark
Other processes don't need to know about faults that they are isolated
from by virtue of address space isolation. They are only interested in
whether some of their state might have been corrupted.
But to be safe, also track unattributed faults. This case should really
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c
b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
index 47b3cf2df230..b24e5475cafb 100644
--- a/drivers
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c
b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
index b24e5475cafb..427c55002f4d
From: Rob Clark
Cancel the timer when the GPU is idle, but also remember to restart it
in the recover path if we've re-submitted submits following the one that
hung.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpu.c | 10 ++
1 file changed, 10 insertions(+)
diff --
From: Rob Clark
Reported-by: Douglas Anderson
Fixes: 9bc95570175a ("drm/msm: Devfreq tuning")
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c
b/drivers/g
From: Rob Clark
Reported-by: Douglas Anderson
Fixes: 9bc95570175a ("drm/msm: Devfreq tuning")
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c
b/drivers/g
From: Rob Clark
It is a 64b register, lets not lose the upper bits.
Fixes: ab5df7b953d8 ("iommu/arm-smmu-qcom: Add an adreno-smmu-priv callback to
get pagefault info")
Signed-off-by: Rob Clark
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 +-
1 file changed, 1 insertion(+),
From: Rob Clark
In particular, we need to ensure all the necessary blocks are switched
to 64b mode (a5xx+) otherwise the high bits of the address of the BO to
snapshot state into will be ignored, resulting in:
*** gpu fault: ttbr0= iova=00012000 dir=READ
type
I stumbled across this thread when I ran into the same issue, while
working out how to move drm/msm to use scheduler's retire +
timeout/recovery (and get rid of our own mirror list of in-flight
jobs). We already have hw error detection enabled, and it can signal
quite fast, so assuming the first j
On Tue, Nov 9, 2021 at 1:07 AM Daniel Vetter wrote:
>
> On Mon, Nov 08, 2021 at 03:39:17PM -0800, Rob Clark wrote:
> > I stumbled across this thread when I ran into the same issue, while
> > working out how to move drm/msm to use scheduler's retire +
> > timeout/rec
From: Rob Clark
This started out as conversion to using drm/sched to handle job timeout,
recovery, and retire (and delete a bunch of code), but the latter part
is on hold until drm/sched is fixed to properly handle job retire/
cleanup before deciding which job triggered the fault/timeout[1
From: Rob Clark
The struct_mutex locking is a remnant from the days before per-obj locks,
and no longer needed.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_debugfs.c | 37 ++-
drivers/gpu/drm/msm/msm_fbdev.c | 13 ---
2 files changed, 16
From: Rob Clark
cur_ctx_seqno already does the same thing, but handles the edge cases
where a refcnt'd context can live after lastclose. So let's not have
two ways to do the same thing.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 3 +--
drivers/gpu/drm/
From: Rob Clark
The remaining struct_mutex usage is just to serialize various gpu
related things (submit/retire/recover/fault/etc), so replace
struct_mutex with gpu->lock.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a5xx_debugfs.c | 4 ++--
drivers/gpu/drm/msm/adr
From: Rob Clark
Add some helpers for fence comparision, which handle rollover properly,
and stop open coding fence seqno comparisions.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_fence.h | 12
drivers/gpu/drm/msm/msm_gpu.c | 6 +++---
drivers/gpu/drm/msm/msm_gpu.h
From: Rob Clark
Add a debugfs interface to ignore hw error irqs, in order to force
fallback to sw hangcheck mechanism. Because the hw error detection is
pretty good on newer gens, we need this for igt tests to test the sw
hang detection.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm
On Wed, Nov 10, 2021 at 7:28 AM Akhil P Oommen wrote:
>
> On 7/28/2021 6:36 AM, Rob Clark wrote:
> > From: Rob Clark
> >
> > Previously the (non-fd) fence returned from submit ioctl was a raw
> > seqno, which is scoped to the ring. But from UABI standpoint, t
On Wed, Nov 10, 2021 at 1:50 AM Daniel Vetter wrote:
>
> On Tue, Nov 09, 2021 at 08:17:01AM -0800, Rob Clark wrote:
> > On Tue, Nov 9, 2021 at 1:07 AM Daniel Vetter wrote:
> > >
> > > On Mon, Nov 08, 2021 at 03:39:17PM -0800, Rob Clark wrote:
> > > > I s
On Thu, Nov 11, 2021 at 7:54 AM Akhil P Oommen wrote:
>
> On 11/10/2021 10:25 PM, Rob Clark wrote:
> > On Wed, Nov 10, 2021 at 7:28 AM Akhil P Oommen
> > wrote:
> >>
> >> On 7/28/2021 6:36 AM, Rob Clark wrote:
> >>> From: Rob Clark
> >>&
From: Rob Clark
A couple of wait_fence related fixes.
Rob Clark (2):
drm/msm: Fix wait_fence submitqueue leak
drm/msm: Restore error return on invalid fence
drivers/gpu/drm/msm/msm_drv.c| 49 ++--
drivers/gpu/drm/msm/msm_gem_submit.c | 1 +
drivers/gpu/drm
From: Rob Clark
We weren't dropping the submitqueue reference in all paths. In
particular, when the fence has already been signalled. Split out
a helper to simplify handling this in the various different return
paths.
Fixes: a61acbbe9cf8 ("drm/msm: Track "seqno" fences by
From: Rob Clark
When converting to use an idr to map userspace fence seqno values back
to a dma_fence, we lost the error return when userspace passes seqno
that is larger than the last submitted fence. Restore this check.
Reported-by: Akhil P Oommen
Fixes: a61acbbe9cf8 ("drm/msm: Track &
From: Rob Clark
Reported-by: kernel test robot
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 8a2af3a27e33..dcde5eff931d
From: Rob Clark
Mesa attempts to allocate a cached-coherent buffer in order to determine
if cached-coherent is supported. Resulting in seeing this error message
once per process with newer mesa. But no reason for this to be more
than a debug msg.
Signed-off-by: Rob Clark
---
drivers/gpu/drm
On Mon, Nov 15, 2021 at 6:43 AM Akhil P Oommen wrote:
>
> On 11/12/2021 12:54 AM, Rob Clark wrote:
> > From: Rob Clark
> >
> > When converting to use an idr to map userspace fence seqno values back
> > to a dma_fence, we lost the error return when userspace passes
From: Rob Clark
This was the one GPU related kernel buffer which was not given a debug
name. Let's fix that.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gp
On Mon, Nov 15, 2021 at 8:16 AM Ondřej Jirman wrote:
>
> On Mon, Nov 15, 2021 at 05:04:36PM +0100, megi xff wrote:
> > On Mon, Nov 15, 2021 at 04:05:02PM +0100, Daniel Vetter wrote:
> > > You need
> > >
> > > commit 13e9e30cafea10dff6bc8d63a38a61249e83fd65
> > > Author: Christian König
> > > Date
On Mon, Nov 15, 2021 at 2:43 PM Rob Clark wrote:
>
> On Mon, Nov 15, 2021 at 8:16 AM Ondřej Jirman wrote:
> >
> > On Mon, Nov 15, 2021 at 05:04:36PM +0100, megi xff wrote:
> > > On Mon, Nov 15, 2021 at 04:05:02PM +0100, Daniel Vetter wrote:
> > &g
From: Rob Clark
drm_sched_job_add_dependency() could drop the last ref, so we need to do
the dma_fence_get() first.
Cc: Christian König
Fixes: 9c2ba265352a drm/scheduler: ("use new iterator in
drm_sched_job_add_implicit_dependencies v2")
Signed-off-by: Rob Clark
---
Applies on t
On Tue, Nov 16, 2021 at 8:37 AM Daniel Vetter wrote:
>
> On Tue, Nov 16, 2021 at 10:25:19AM +0100, Christian König wrote:
> > We need to grab another ref before trying to add the fence to the sched
> > job and not after.
> >
> > Signed-off-by: Christian König
>
> Reviewed-by: Daniel Vetter
>
> I
On Wed, Nov 17, 2021 at 5:23 PM Steev Klimaszewski wrote:
>
>
> On 11/17/21 1:27 AM, Christian König wrote:
> > Am 16.11.21 um 19:30 schrieb Amit Pundir:
> >> On Tue, 16 Nov 2021 at 21:21, Rob Clark wrote:
> >>> From: Rob Clark
> >>>
> >>
On Fri, Oct 22, 2021 at 4:35 AM Dmitry Baryshkov
wrote:
>
> Hi,
>
> On Fri, 22 Oct 2021 at 02:53, wrote:
> >
> > On 2021-09-30 07:00, Dmitry Baryshkov wrote:
> > > In preparations of virtualizing the dpu_plane rip out debugfs support
> > > from dpu_plane (as it is mostly used to expose plane's pi
On Thu, Nov 18, 2021 at 2:39 AM Pekka Paalanen wrote:
>
> On Wed, 17 Nov 2021 14:48:40 -0800
> Brian Norris wrote:
>
> > A variety of applications have found it useful to listen to
> > user-initiated input events to make decisions within a DRM driver, given
> > that input events are often the fir
On Fri, Nov 19, 2021 at 1:54 AM Pekka Paalanen wrote:
>
> On Thu, 18 Nov 2021 15:30:38 -0800
> Rob Clark wrote:
>
> > On Thu, Nov 18, 2021 at 2:39 AM Pekka Paalanen wrote:
> > >
> > > On Wed, 17 Nov 2021 14:48:40 -0800
> > > Brian Norris wrote:
On Thu, Nov 18, 2021 at 12:53 AM Daniel Vetter wrote:
>
> On Tue, Nov 16, 2021 at 06:31:10PM -0800, Gurchetan Singh wrote:
> > On Tue, Nov 16, 2021 at 7:43 AM Daniel Vetter wrote:
> >
> > > On Mon, Nov 15, 2021 at 07:26:14PM +, Kasireddy, Vivek wrote:
> > > > Hi Daniel, Greg,
> > > >
> > > >
From: Rob Clark
Re-work the boost and idle clamping to use PM QoS requests instead, so
they get aggreggated with other requests (such as cooling device).
This does have the minor side-effect that devfreq sysfs min_freq/
max_freq files now reflect the boost and idle clamping, as they show
From: Rob Clark
This was supposed to be a relative timer, not absolute.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c
b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
index
On Fri, Nov 19, 2021 at 2:46 PM Rob Clark wrote:
>
> From: Rob Clark
>
> This was supposed to be a relative timer, not absolute.
>
Fixes: 658f4c829688 ("drm/msm/devfreq: Add 1ms delay before clamping freq")
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm
On Fri, Nov 19, 2021 at 4:21 PM Doug Anderson wrote:
>
> Hi,
>
> On Fri, Nov 19, 2021 at 2:47 PM Rob Clark wrote:
> >
> > +void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor)
> > +{
> > + struct msm_gpu_devfreq *df = &gpu-
From: Rob Clark
This was supposed to be a relative timer, not absolute.
Fixes: 658f4c829688 ("drm/msm/devfreq: Add 1ms delay before clamping freq")
Signed-off-by: Rob Clark
Reviewed-by: Douglas Anderson
---
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +-
1 file changed, 1 inser
From: Rob Clark
Looks like 658f4c829688 ("drm/msm/devfreq: Add 1ms delay before
clamping freq") was badly rebased on top of efb8a170a367 ("drm/msm:
Fix devfreq NULL pointer dereference on a3xx") and ended up with
the NULL check in the wrong place.
Fixes: 658f4c829688 ("
From: Rob Clark
Re-work the boost and idle clamping to use PM QoS requests instead, so
they get aggreggated with other requests (such as cooling device).
This does have the minor side-effect that devfreq sysfs min_freq/
max_freq files now reflect the boost and idle clamping, as they show
On Thu, Nov 18, 2021 at 2:21 AM Akhil P Oommen wrote:
>
> Capture gmu log in coredump to enhance debugging.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 41
> +
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
> driv
On Mon, Nov 22, 2021 at 10:26 AM Rob Clark wrote:
>
> On Thu, Nov 18, 2021 at 2:21 AM Akhil P Oommen wrote:
> >
> > Capture gmu log in coredump to enhance debugging.
> >
> > Signed-off-by: Akhil P Oommen
> > ---
> >
> >
From: Rob Clark
This adds additional snapshotting for interesting GMU buffers to the
devcore dumps, adds a couple WARN_ON()s, etc. (Plus a bonus comment)
Akhil P Oommen (1):
drm/msm/a6xx: Capture gmu log in devcoredump
Rob Clark (6):
drm/msm/gpu: Name GMU bos
drm/msm/gpu: Add some
From: Akhil P Oommen
Capture gmu log in coredump to enhance debugging.
Signed-off-by: Akhil P Oommen
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 41 +
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno
From: Rob Clark
This was supposed to be a relative timer, not absolute.
Fixes: 658f4c829688 ("drm/msm/devfreq: Add 1ms delay before clamping freq")
Signed-off-by: Rob Clark
Reviewed-by: Douglas Anderson
---
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +-
1 file changed, 1 inser
From: Rob Clark
Looks like 658f4c829688 ("drm/msm/devfreq: Add 1ms delay before
clamping freq") was badly rebased on top of efb8a170a367 ("drm/msm:
Fix devfreq NULL pointer dereference on a3xx") and ended up with
the NULL check in the wrong place.
Fixes: 658f4c829688 ("
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 71e52b2b2025..e1774ea342b1 100644
From: Rob Clark
Re-work the boost and idle clamping to use PM QoS requests instead, so
they get aggreggated with other requests (such as cooling device).
This does have the minor side-effect that devfreq sysfs min_freq/
max_freq files now reflect the boost and idle clamping, as they show
From: Rob Clark
We don't expect either of these conditions to ever be true, so let's get
shouty if they are.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drive
From: Rob Clark
Turn it into a thing we can use to snapshot other GMU buffers.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 34 +
1 file changed, 15 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
b
From: Rob Clark
This also includes a history of start index of the last 8 messages on
each queue, since parsing backwards to decode recently sent HFI messages
is hard(ish).
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 48 -
drivers/gpu/drm/msm
From: Rob Clark
It appears to be a GMU fw build option whether it does anything with
debug and log buffers, but if they are all zeros it won't add anything
to the devcore size.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 12
1 file change
From: Rob Clark
If you don't realize is_a650_family() also encompasses a660 family,
you'd think that the debug buffer is double allocated. Add a comment
to make this more clear.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 3 +++
1 file changed, 3 insertion
On Wed, Nov 24, 2021 at 11:36 PM Dmitry Baryshkov
wrote:
>
> On 28/04/2021 22:36, Rob Clark wrote:
> > From: Rob Clark
> >
> > Currently if userspace manages to fill up the ring faster than the GPU
> > can consume we (a) spin for up to 1sec, and then (b) overwri
that caused crashes
Philip Chen (1):
drm/msm/dsi: set default num_data_lanes
Rob Clark (8):
drm/msm/devfreq: Fix OPP refcnt leak
drm/msm: Fix wait_fence submitqueue leak
drm/msm: Restore error return on invalid fence
drm/msm: Make a6xx_gpu_set_freq() static
drm
From: Rob Clark
Elsewhere we treat zero as "no fence" and __msm_gem_submit_destroy()
skips removal from fence_idr. We could alternately change this to use
negative values for "no fence" but I think it is more clear to not allow
zero as a valid fence_id.
Signed-off-by: Rob
On Mon, Nov 29, 2021 at 10:18 AM Rob Clark wrote:
>
> From: Rob Clark
>
> Elsewhere we treat zero as "no fence" and __msm_gem_submit_destroy()
> skips removal from fence_idr. We could alternately change this to use
> negative values for "no fence" but
From: Rob Clark
Otherwise we don't get another shot at it if the bridge probes before
the dsi host is registered. It seems like this is what *most* (but not
all) of the other bridges do.
It looks like this was missed in the conversion to attach dsi host at
probe time.
Fixes: c3b75d4
From: Rob Clark
Otherwise we don't get another shot at it if the bridge probes before
the dsi host is registered. It seems like this is what *most* (but not
all) of the other bridges do.
It looks like this was missed in the conversion to attach dsi host at
probe time.
Fixes: c3b75d4
From: Rob Clark
Otherwise we don't get another shot at it if the bridge probes before
the dsi host is registered. It seems like this is what *most* (but not
all) of the other bridges do.
It looks like this was missed in the conversion to attach dsi host at
probe time.
Fixes: c3b75d4
On Thu, Nov 4, 2021 at 8:04 PM Sean Paul wrote:
>
> From: Sean Paul
>
> Just me with another revision of HDCP support for msm.
>
> This v4 patch series is mostly a retread of v3 with the following
> changes:
> - rebased on Bjorn's displayport-controller register refactor
> - another change to the
On Wed, Dec 8, 2021 at 10:01 AM Dmitry Baryshkov
wrote:
>
> msm_ioremap() functions take additional argument dbgname used to output
> single debug line telling IO range. Drop that extra argument, use
> resource name instead.
For some history, the dbgname traces were used by an older tool that
cou
On Thu, Nov 4, 2021 at 8:05 PM Sean Paul wrote:
>
> From: Sean Paul
>
> This patch adds the register ranges required for HDCP key injection and
> HDCP TrustZone interaction as described in the dt-bindings for the
> sc7180 dp controller. Now that these are supported, change the
> compatible string
From: Rob Clark
I am seeing some crash logs which imply that we are trying to use
crashdumper hw to read back GPU state when the GPU isn't initialized.
This doesn't go well (for example, GPU could be in 32b address mode
and ignoring the upper bits of buffer that it is trying to dum
From: Rob Clark
This series adds a "kms" debugfs file to dump display register + atomic
state, which is useful for debugging issues that don't trigger a display
error irq (such as dsi phy misconfiguration).
Rob Clark (3):
drm/msm/disp: Tweak display snapshot to match gpu sna
From: Rob Clark
Add UTS_RELEASE and show timestamp the same way for consistency.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/disp/msm_disp_snapshot.h | 4 ++--
drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c | 9 ++---
2 files changed, 8 insertions(+), 5 deletions(-)
diff
From: Rob Clark
We'll re-use this for debugfs.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/disp/msm_disp_snapshot.c | 28 +++-
drivers/gpu/drm/msm/disp/msm_disp_snapshot.h | 10 +++
2 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/dr
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_debugfs.c | 90 +++
1 file changed, 90 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_debugfs.c
b/drivers/gpu/drm/msm/msm_debugfs.c
index 956b1efc3721..088f1160c892 100644
--- a/drivers/gpu
On Mon, Dec 14, 2020 at 3:41 AM Kalyan Thota wrote:
>
> Turn off vblank irqs immediately as soon as drm_vblank_put is
> requested so that there are no irqs triggered during idle state.
>
> This will reduce cpu wakeups and help in power saving. The change
> also enable driver timestamp for vblanks.
On Sat, Jan 2, 2021 at 12:26 PM Iskren Chernev wrote:
>
> The msm_gem_get_iova should be guarded with gpu != NULL and not aspace
> != NULL, because aspace is NULL when using vram carveout.
>
> Fixes: 933415e24bd0d ("drm/msm: Add support for private address space
> instances")
>
> Signed-off-by: I
On Wed, Jan 6, 2021 at 8:50 PM Sai Prakash Ranjan
wrote:
>
> On 2021-01-05 01:00, Konrad Dybcio wrote:
> > Using this code on A5xx (and probably older too) causes a
> > smmu bug.
> >
> > Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system
> > cache(LLC)")
> > Signed-off-by: Konrad Dyb
connection pending state
Rob Clark (1):
drm/msm: Fix WARN_ON() splat in _free_object()
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 6 --
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 6 --
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 6 --
drivers/gpu/drm/msm/adreno/adreno_device.c
On Thu, Jan 7, 2021 at 9:20 AM Rob Clark wrote:
>
> On Sat, Jan 2, 2021 at 12:26 PM Iskren Chernev
> wrote:
> >
> > The msm_gem_get_iova should be guarded with gpu != NULL and not aspace
> > != NULL, because aspace is NULL when using vram carveout.
> >
> &
On Fri, Jan 8, 2021 at 6:05 AM Sai Prakash Ranjan
wrote:
>
> On 2021-01-08 19:09, Konrad Dybcio wrote:
> >> Konrad, can you please test this below change without your change?
> >
> > This brings no difference, a BUG still happens. We're still calling
> > to_a6xx_gpu on ANY device that's probed! To
From: Rob Clark
This series adds a "kms" debugfs file to dump display register + atomic
state, which is useful for debugging issues that don't trigger a display
error irq (such as dsi phy misconfiguration).
Rob Clark (3):
drm/msm/disp: Tweak display snapshot to match gpu sna
From: Rob Clark
Add UTS_RELEASE and show timestamp the same way for consistency.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/disp/msm_disp_snapshot.h | 4 ++--
drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c | 9 ++---
2 files changed, 8 insertions(+), 5 deletions(-)
diff
From: Rob Clark
We'll re-use this for debugfs.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/disp/msm_disp_snapshot.c | 28 +++-
drivers/gpu/drm/msm/disp/msm_disp_snapshot.h | 10 +++
2 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/dr
From: Rob Clark
Signed-off-by: Rob Clark
---
v2: Drop unneeded msm_kms_show_priv [Dmitry B]
drivers/gpu/drm/msm/msm_debugfs.c | 75 +++
1 file changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_debugfs.c
b/drivers/gpu/drm/msm/msm_debugfs.c
index
501 - 600 of 6052 matches
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