From: Rob Clark
Somehow we had neither ->wait() nor dma_fence_signal() calls, and no
one noticed. Oops.
Note that this removes the !timeout case, which has not been used in
a long time.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_fence.c | 59 +++--
On Tue, Jul 20, 2021 at 11:03 AM Christian König
wrote:
>
> Hi Rob,
>
> Am 20.07.21 um 17:07 schrieb Rob Clark:
> > From: Rob Clark
> >
> > Somehow we had neither ->wait() nor dma_fence_signal() calls, and no
> > one noticed. Oops.
>
>
> I'
On Tue, Jul 20, 2021 at 1:55 PM Daniel Vetter wrote:
>
> On Tue, Jul 20, 2021 at 8:26 PM Rob Clark wrote:
> >
> > On Tue, Jul 20, 2021 at 11:03 AM Christian König
> > wrote:
> > >
> > > Hi Rob,
> > >
> > > Am 20.07.21 um 17:07 schrieb
On Wed, Jul 21, 2021 at 12:59 AM Daniel Vetter wrote:
>
> On Wed, Jul 21, 2021 at 12:32 AM Rob Clark wrote:
> >
> > On Tue, Jul 20, 2021 at 1:55 PM Daniel Vetter wrote:
> > >
> > > On Tue, Jul 20, 2021 at 8:26 PM Rob Clark wrote:
> > > >
> >
On Thu, Jul 22, 2021 at 1:42 AM Christian König
wrote:
>
> Am 21.07.21 um 21:03 schrieb Daniel Vetter:
> > On Wed, Jul 21, 2021 at 09:34:43AM -0700, Rob Clark wrote:
> >> On Wed, Jul 21, 2021 at 12:59 AM Daniel Vetter wrote:
> >>> On Wed, Jul 21, 2021 at 12:32 A
On Thu, Jul 22, 2021 at 2:28 AM Christian König
wrote:
>
> Am 22.07.21 um 11:08 schrieb Daniel Vetter:
> > [SNIP]
> >> As far as I know wake_up_state() tries to run the thread on the CPU it was
> >> scheduled last, while wait_event_* makes the thread run on the CPU who
> >> issues the wake by defa
From: Rob Clark
This is the outcome of trying to fix some bad gpu freq behavior seen in
some use-cases, in particular mobile games that throttle themselves to
30fps. With the existing tuning, we'd end up spending most of the time
that we should be running fast at a low freq, and most o
From: Rob Clark
Before we start adding more cleverness, split it into it's own file.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +-
drivers/gpu/drm/msm/msm_gpu.c | 116 +-
drivers/gp
From: Rob Clark
In the next patch, it grows a bit more, so lets not duplicate the logic
in multiple places.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm
From: Rob Clark
This adds a few things to try and make frequency scaling better match
the workload:
1) Longer polling interval to avoid whip-lashing between too-high and
too-low frequencies in certain workloads, like mobile games which
throttle themselves to 30fps.
Previously our
()
On Fri, Jul 23, 2021 at 3:38 AM Akhil P Oommen wrote:
>
> This patch adds support for the gpu found in the Snapdragon 7c Gen 3
> compute platform. This gpu is similar to the exisiting a660 gpu with
> minor delta in the programing sequence. As the Adreno GPUs are moving
> away from a numeric ch
From: Rob Clark
A couple tweaks to reduce fence signal latency.
Rob Clark (2):
drm/msm: Let fences read directly from memptrs
drm/msm: Signal fences sooner
drivers/gpu/drm/msm/msm_fence.c | 11 +--
drivers/gpu/drm/msm/msm_fence.h | 41 +++---
drivers/gpu
From: Rob Clark
Let dma_fence::signaled, etc, read directly from the address that the hw
is writing with updated completed fence seqno, so we can potentially
notice that the fence is signaled sooner.
Plus add some docs.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_fence.c | 11
From: Rob Clark
Nothing we do to in update_fences() can't be done in an atomic context,
so move this into the GPU's irq context to reduce latency (and call
dma_fence_signal() so we aren't relying on dma_fence_is_signaled() which
would defeat the purpose).
Signed-off-by: Rob Clar
From: Rob Clark
This is the outcome of trying to fix some bad gpu freq behavior seen in
some use-cases, in particular mobile games that throttle themselves to
30fps. With the existing tuning, we'd end up spending most of the time
that we should be running fast at a low freq, and most o
From: Rob Clark
Before we start adding more cleverness, split it into it's own file.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +-
drivers/gpu/drm/msm/msm_gpu.c | 116 +-
drivers/gp
From: Rob Clark
In the next patch, it grows a bit more, so lets not duplicate the logic
in multiple places.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm
From: Rob Clark
This adds a few things to try and make frequency scaling better match
the workload:
1) Longer polling interval to avoid whip-lashing between too-high and
too-low frequencies in certain workloads, like mobile games which
throttle themselves to 30fps.
Previously our
From: Rob Clark
Conversion to gpu_scheduler, and bonus removal of
drm_gem_object_put_locked()
v2: Fix priority mixup (msm UAPI has lower numeric priority value as
higher priority, inverse of drm/scheduler) and add some comments
in the UAPI header to clarify.
Now that we move active
From: Rob Clark
Fix a couple incorrect or misspelt comments, and add submitqueue doc
comment.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_gem.h | 3 +--
drivers/gpu/drm/msm/msm_gem_submit.c | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 15
From: Rob Clark
If we don't have a gpu, there is no need to create a submitqueue, which
lets us simplify the error handling and submitqueue creation.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_submitqueue.c | 22 +++---
1 file change
From: Rob Clark
No idea why we were still using this. It certainly hasn't been needed
for some time. So drop the pointless twin codepaths.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/adreno/a5xx_debugfs.c | 4 +-
drivers/gpu/drm/msm/adreno/a5xx_
From: Rob Clark
Now that no one is using it, remove it.
Signed-off-by: Rob Clark
Acked-by: Christian König
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_gem.c | 22 --
include/drm/drm_gem.h | 2 --
2 files changed, 24 deletions(-)
diff --git a/drivers/gpu/drm
From: Rob Clark
Move all the locked/active/pinned state handling to msm_gem_submit.c.
In particular, for drm/scheduler, we'll need to do all this before
pushing the submit job to the scheduler. But while we're at it we can
get rid of the dupicate pin and refcnt.
Signed-off-by: Rob Cl
From: Rob Clark
In the next patch, we start having more than a single potential failure
reason.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_gem_submit.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu
From: Rob Clark
No need for this to be split in two parts.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_gem_submit.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm
From: Rob Clark
For existing adrenos, there is one or more ringbuffer, depending on
whether preemption is supported. When preemption is supported, each
ringbuffer has it's own priority. A submitqueue (which maps to a
gl context or vk queue in userspace) is mapped to a specific ring-
buff
From: Rob Clark
It is sufficient to serialize on the submit queue now.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_gem_submit.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers
From: Rob Clark
Previously the (non-fd) fence returned from submit ioctl was a raw
seqno, which is scoped to the ring. But from UABI standpoint, the
ioctls related to seqno fences all specify a submitqueue. We can
take advantage of that to replace the seqno fences with a cyclic idr
handle
From: Rob Clark
The drm/scheduler provides additional prioritization on top of that
provided by however many number of ringbuffers (each with their own
priority level) is supported on a given generation. Expose the
additional levels of priority to userspace and map the userspace
priority back
From: Rob Clark
Mark all the bos in the submit as active, before pinning, to prevent
evicting a buffer in the same submit to make room for a buffer earlier
in the table.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c| 2 --
drivers/gpu/drm/msm/msm_gem_submit.c | 28
From: Rob Clark
Based on discussion from a previous series[1] to add a "boost" mechanism
when, for example, vblank deadlines are missed. Instead of a boost
callback, this approach adds a way to set a deadline on the fence, by
which the waiter would like to see the fence signalled.
I&
From: Rob Clark
Add a way to hint to the fence signaler of an upcoming deadline, such as
vblank, which the fence waiter would prefer not to miss. This is to aid
the fence signaler in making power management decisions, like boosting
frequency as the deadline approaches and awareness of missing
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/drm_vblank.c | 31 +++
include/drm/drm_vblank.h | 1 +
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 3417e1ac7918..88c824c294dc
From: Rob Clark
For an atomic commit updating a single CRTC (ie. a pageflip) calculate
the next vblank time, and inform the fence(s) of that deadline.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/drm_atomic_helper.c | 36 +
1 file changed, 36 insertions(+)
diff
From: Rob Clark
As the finished fence is the one that is exposed to userspace, and
therefore the one that other operations, like atomic update, would
block on, we need to propagate the deadline from from the finished
fence to the actual hw fence.
Signed-off-by: Rob Clark
---
drivers/gpu/drm
On Mon, Jul 26, 2021 at 4:34 PM Rob Clark wrote:
>
> From: Rob Clark
>
> Based on discussion from a previous series[1] to add a "boost" mechanism
> when, for example, vblank deadlines are missed. Instead of a boost
> callback, this approach adds a way to set a deadl
On Tue, Jul 27, 2021 at 12:11 AM Christian König
wrote:
>
> Am 27.07.21 um 01:38 schrieb Rob Clark:
> > From: Rob Clark
> >
> > Add a way to hint to the fence signaler of an upcoming deadline, such as
> > vblank, which the fence waiter would prefer not to miss.
On Tue, Jul 27, 2021 at 3:44 AM Michel Dänzer wrote:
>
> On 2021-07-27 1:38 a.m., Rob Clark wrote:
> > From: Rob Clark
> >
> > For an atomic commit updating a single CRTC (ie. a pageflip) calculate
> > the next vblank time, and inform the fence(s) of that deadli
On Tue, Jul 27, 2021 at 7:50 AM Michel Dänzer wrote:
>
> On 2021-07-27 1:38 a.m., Rob Clark wrote:
> > From: Rob Clark
> >
> > Based on discussion from a previous series[1] to add a "boost" mechanism
> > when, for example, vblank deadlines are missed
On Tue, Jul 27, 2021 at 8:19 AM Michel Dänzer wrote:
>
> On 2021-07-27 5:12 p.m., Rob Clark wrote:
> > On Tue, Jul 27, 2021 at 7:50 AM Michel Dänzer wrote:
> >>
> >> On 2021-07-27 1:38 a.m., Rob Clark wrote:
> >>> From: Rob Clark
> >>>
>
io plugged change at dp_pm_resume
Rob Clark (1):
drm/msm: Fix display fault handling
Robert Foss (1):
drm/msm/dpu: Fix sm8250_mdp register length
Sean Paul (1):
drm/msm/dp: Initialize dp->aux->drm_dev before registration
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2
From: Rob Clark
Conversion to gpu_scheduler, and bonus removal of
drm_gem_object_put_locked()
v2: Fix priority mixup (msm UAPI has lower numeric priority value as
higher priority, inverse of drm/scheduler) and add some comments
in the UAPI header to clarify.
Now that we move active
From: Rob Clark
Fix a couple incorrect or misspelt comments, and add submitqueue doc
comment.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_gem.h | 3 +--
drivers/gpu/drm/msm/msm_gem_submit.c | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 15
From: Rob Clark
If we don't have a gpu, there is no need to create a submitqueue, which
lets us simplify the error handling and submitqueue creation.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_submitqueue.c | 22 +++---
1 file change
From: Rob Clark
No idea why we were still using this. It certainly hasn't been needed
for some time. So drop the pointless twin codepaths.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/adreno/a5xx_debugfs.c | 4 +-
drivers/gpu/drm/msm/adreno/a5xx_
From: Rob Clark
No need for this to be split in two parts.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_gem_submit.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm
From: Rob Clark
Now that no one is using it, remove it.
Signed-off-by: Rob Clark
Acked-by: Christian König
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_gem.c | 22 --
include/drm/drm_gem.h | 2 --
2 files changed, 24 deletions(-)
diff --git a/drivers/gpu/drm
From: Rob Clark
Move all the locked/active/pinned state handling to msm_gem_submit.c.
In particular, for drm/scheduler, we'll need to do all this before
pushing the submit job to the scheduler. But while we're at it we can
get rid of the dupicate pin and refcnt.
Signed-off-by: Rob Cl
From: Rob Clark
Previously the (non-fd) fence returned from submit ioctl was a raw
seqno, which is scoped to the ring. But from UABI standpoint, the
ioctls related to seqno fences all specify a submitqueue. We can
take advantage of that to replace the seqno fences with a cyclic idr
handle
From: Rob Clark
In the next patch, we start having more than a single potential failure
reason.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_gem_submit.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu
From: Rob Clark
This was only used to detect userspace including the same bo multiple
times in a submit. But ww_mutex can already tell us this.
When we drop struct_mutex around the submit ioctl, we'd otherwise need
to lock the bo before adding it to the bo_list. But since ww_mutex can
al
From: Rob Clark
It is sufficient to serialize on the submit queue now.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_gem_submit.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers
From: Rob Clark
For existing adrenos, there is one or more ringbuffer, depending on
whether preemption is supported. When preemption is supported, each
ringbuffer has it's own priority. A submitqueue (which maps to a
gl context or vk queue in userspace) is mapped to a specific ring-
buff
From: Rob Clark
The drm/scheduler provides additional prioritization on top of that
provided by however many number of ringbuffers (each with their own
priority level) is supported on a given generation. Expose the
additional levels of priority to userspace and map the userspace
priority back
From: Rob Clark
Mark all the bos in the submit as active, before pinning, to prevent
evicting a buffer in the same submit to make room for a buffer earlier
in the table.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c| 2 --
drivers/gpu/drm/msm/msm_gem_submit.c | 28
From: Rob Clark
Signed-off-by: Rob Clark
---
This is a quick implementation of what I had in mind for driver side
of deadline boost. For a couple games with bad gpu devfreq behavior
this boosts "Render quality" from ~35% to ~95%. (The "Render quality"
metric in chrome://
From: Rob Clark
Conversion to gpu_scheduler, and bonus removal of
drm_gem_object_put_locked()
v2: Fix priority mixup (msm UAPI has lower numeric priority value as
higher priority, inverse of drm/scheduler) and add some comments
in the UAPI header to clarify.
Now that we move active
From: Rob Clark
If we don't have a gpu, there is no need to create a submitqueue, which
lets us simplify the error handling and submitqueue creation.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_submitqueue.c | 22 +++---
1 file change
From: Rob Clark
Fix a couple incorrect or misspelt comments, and add submitqueue doc
comment.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_gem.h | 3 +--
drivers/gpu/drm/msm/msm_gem_submit.c | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 15
From: Rob Clark
No idea why we were still using this. It certainly hasn't been needed
for some time. So drop the pointless twin codepaths.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/adreno/a5xx_debugfs.c | 4 +-
drivers/gpu/drm/msm/adreno/a5xx_
From: Rob Clark
Now that no one is using it, remove it.
Signed-off-by: Rob Clark
Acked-by: Christian König
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_gem.c | 22 --
include/drm/drm_gem.h | 2 --
2 files changed, 24 deletions(-)
diff --git a/drivers/gpu/drm
From: Rob Clark
No need for this to be split in two parts.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_gem_submit.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm
From: Rob Clark
Move all the locked/active/pinned state handling to msm_gem_submit.c.
In particular, for drm/scheduler, we'll need to do all this before
pushing the submit job to the scheduler. But while we're at it we can
get rid of the dupicate pin and refcnt.
Signed-off-by: Rob Cl
From: Rob Clark
Previously the (non-fd) fence returned from submit ioctl was a raw
seqno, which is scoped to the ring. But from UABI standpoint, the
ioctls related to seqno fences all specify a submitqueue. We can
take advantage of that to replace the seqno fences with a cyclic idr
handle
From: Rob Clark
This was only used to detect userspace including the same bo multiple
times in a submit. But ww_mutex can already tell us this.
When we drop struct_mutex around the submit ioctl, we'd otherwise need
to lock the bo before adding it to the bo_list. But since ww_mutex can
al
From: Rob Clark
For existing adrenos, there is one or more ringbuffer, depending on
whether preemption is supported. When preemption is supported, each
ringbuffer has it's own priority. A submitqueue (which maps to a
gl context or vk queue in userspace) is mapped to a specific ring-
buff
From: Rob Clark
It is sufficient to serialize on the submit queue now.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_gem_submit.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers
From: Rob Clark
In the next patch, we start having more than a single potential failure
reason.
Signed-off-by: Rob Clark
Acked-by: Christian König
---
drivers/gpu/drm/msm/msm_gem_submit.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu
From: Rob Clark
The drm/scheduler provides additional prioritization on top of that
provided by however many number of ringbuffers (each with their own
priority level) is supported on a given generation. Expose the
additional levels of priority to userspace and map the userspace
priority back
From: Rob Clark
Mark all the bos in the submit as active, before pinning, to prevent
evicting a buffer in the same submit to make room for a buffer earlier
in the table.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c| 2 --
drivers/gpu/drm/msm/msm_gem_submit.c | 28
On Wed, Jul 28, 2021 at 4:37 AM Christian König
wrote:
>
> Am 28.07.21 um 09:03 schrieb Christian König:
> > Am 27.07.21 um 16:25 schrieb Rob Clark:
> >> On Tue, Jul 27, 2021 at 12:11 AM Christian König
> >> wrote:
> >>> Am 27.07.21 um 01:38
On Wed, Jul 28, 2021 at 6:57 AM Pekka Paalanen wrote:
>
> On Wed, 28 Jul 2021 15:31:41 +0200
> Christian König wrote:
>
> > Am 28.07.21 um 15:24 schrieb Michel Dänzer:
> > > On 2021-07-28 3:13 p.m., Christian König wrote:
> > >> Am 28.07.21 um 15:08 schrieb Michel Dänzer:
> > >>> On 2021-07-28 1:
On Wed, Jul 28, 2021 at 6:24 AM Michel Dänzer wrote:
>
> On 2021-07-28 3:13 p.m., Christian König wrote:
> > Am 28.07.21 um 15:08 schrieb Michel Dänzer:
> >> On 2021-07-28 1:36 p.m., Christian König wrote:
> >>> Am 27.07.21 um 17:37 schrieb Rob Clark:
> >>
On Wed, Jul 28, 2021 at 10:23 AM Christian König
wrote:
>
>
>
> Am 28.07.21 um 17:15 schrieb Rob Clark:
> > On Wed, Jul 28, 2021 at 4:37 AM Christian König
> > wrote:
> >> Am 28.07.21 um 09:03 schrieb Christian König:
> >>> Am 27.07.21 um 16:25 schr
09:19:00 -0700)
--------
Rob Clark (18):
drm/msm: Let fences read directly from memptrs
drm/msm: Signal fences sooner
drm/msm: Split out devfreq handling
drm/msm: Split out get_freq() helper
drm/msm: Devfreq tuning
drm/msm:
shortly after reaching UI with the following errors:
>
> https://paste.ubuntu.com/p/HvjmzZYtgw/
>
> I did a git bisect and the patch ("drm/msm: Devfreq tuning") seems to be
> the cause of the crash, reverting it resolves the issue.
>
>
> On 28/07/2021 21:52, Rob Clark
On Wed, Jul 28, 2021 at 7:18 PM Caleb Connolly
wrote:
>
>
>
> On 29/07/2021 02:02, Rob Clark wrote:
> > Jordan, any idea if more frequent frequency changes would for some
> > reason make a630 grumpy? I was expecting it should be somewhat
> > similar to a618 (same
On Thu, Jul 29, 2021 at 12:03 AM Daniel Vetter wrote:
>
> On Wed, Jul 28, 2021 at 10:58:51AM -0700, Rob Clark wrote:
> > On Wed, Jul 28, 2021 at 10:23 AM Christian König
> > wrote:
> > >
> > >
> > >
> > > Am 28.07.21 um 17:15 schrieb Rob Cl
On Thu, Jul 29, 2021 at 7:33 AM Akhil P Oommen wrote:
>
> Use rev instead of revn to identify the SKU. This is in
> preparation to the introduction of 7c3 gpu which won't have a
> revn.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> (no changes since v1)
>
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c |
On Thu, Jul 29, 2021 at 8:21 AM Akhil P Oommen wrote:
>
> This patch adds support for the gpu found in the Snapdragon 7c Gen 3
> compute platform. This gpu is similar to the exisiting a660 gpu with
> minor delta in the programing sequence. As the Adreno GPUs are moving
> away from a numeric chipid
On Thu, Jul 29, 2021 at 8:36 AM Akhil P Oommen wrote:
>
> On 7/29/2021 8:57 PM, Rob Clark wrote:
> > On Thu, Jul 29, 2021 at 7:33 AM Akhil P Oommen
> > wrote:
> >>
> >> Use rev instead of revn to identify the SKU. This is in
> >> preparation to t
On Thu, Jul 29, 2021 at 8:31 AM Akhil P Oommen wrote:
>
> Introduce a feature flag in gpulist to easily identify the capabilities
> of each gpu revision. This will help to avoid a lot of adreno_is_axxx()
> check when we add new features. In the current patch, HW APRIV feature
> is converted to a f
On Thu, Jul 29, 2021 at 9:18 AM Daniel Vetter wrote:
>
> On Thu, Jul 29, 2021 at 5:19 PM Rob Clark wrote:
> >
> > On Thu, Jul 29, 2021 at 12:03 AM Daniel Vetter wrote:
> > >
> > > On Wed, Jul 28, 2021 at 10:58:51AM -0700, Rob Clark wrote:
> > > >
On Thu, Jul 29, 2021 at 10:19 AM Stephen Boyd wrote:
>
> Quoting Akhil P Oommen (2021-07-28 04:54:01)
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > index 029723a..c88f366 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > +++ b/arch/ar
From: Rob Clark
The more frequent frequency transitions resulting from clamping freq to
minimum when the GPU is idle seems to be causing some issue with the bus
getting voted off when it should be on. (An enable racing with an async
disable?) This might be a problem outside of the GPU, as I
27;m dropping), since there
is nothing stopping other workloads from hitting higher OPPs.
I'm slightly curious why I didn't have problems at higher OPPs on my
c630 laptop (sdm850)
BR,
-R
>
> On 29/07/2021 19:39, Rob Clark wrote:
> > From: Rob Clark
> >
> > The mor
On Thu, Jul 29, 2021 at 1:28 PM Caleb Connolly
wrote:
>
>
>
> On 29/07/2021 21:24, Rob Clark wrote:
> > On Thu, Jul 29, 2021 at 1:06 PM Caleb Connolly
> > wrote:
> >>
> >> Hi Rob,
> >>
> >> I've done some more testing! It looks
On Sat, Jul 24, 2021 at 8:21 PM Bjorn Andersson
wrote:
>
> This patch adds a Adreno 680 entry to the gpulist.
Looks reasonable, but I wonder if we should just go ahead and add
adreno_is_a640_family() in a similar vein to
adreno_is_a650_familiy()/adreno_is_a660_family().. I think most of the
'if (
On Thu, Jul 29, 2021 at 8:53 PM Akhil P Oommen wrote:
>
> On 7/30/2021 5:38 AM, Rob Clark wrote:
> > On Sat, Jul 24, 2021 at 8:21 PM Bjorn Andersson
> > wrote:
> >>
> >> This patch adds a Adreno 680 entry to the gpulist.
> >
> > Looks reasonable,
On Mon, Aug 2, 2021 at 3:55 AM Will Deacon wrote:
>
> On Thu, Jul 29, 2021 at 10:08:22AM +0530, Sai Prakash Ranjan wrote:
> > On 2021-07-28 19:30, Georgi Djakov wrote:
> > > On Mon, Jan 11, 2021 at 07:45:02PM +0530, Sai Prakash Ranjan wrote:
> > > > commit ecd7274fb4cd ("iommu: Remove unused IOMMU
On Mon, Aug 2, 2021 at 8:14 AM Will Deacon wrote:
>
> On Mon, Aug 02, 2021 at 08:08:07AM -0700, Rob Clark wrote:
> > On Mon, Aug 2, 2021 at 3:55 AM Will Deacon wrote:
> > >
> > > On Thu, Jul 29, 2021 at 10:08:22AM +0530, Sai Prakash Ranjan wrote:
> > > >
On Tue, Aug 3, 2021 at 2:37 AM Dmitry Baryshkov
wrote:
>
> On 03/08/2021 12:06, Thomas Zimmermann wrote:
> > Drop the DRM IRQ midlayer in favor of Linux IRQ interfaces. DRM's
> > IRQ helpers are mostly useful for UMS drivers. Modern KMS drivers
> > don't benefit from using it.
> >
> > DRM IRQ call
On Thu, Apr 8, 2021 at 4:15 AM Daniel Vetter wrote:
>
> On Mon, Apr 05, 2021 at 10:45:23AM -0700, Rob Clark wrote:
> > From: Rob Clark
> >
> > One would normally hope not to be under enough memory pressure to need
> > to swap GEM objects to disk backed swap. But m
On Wed, Apr 7, 2021 at 12:11 PM AngeloGioacchino Del Regno
wrote:
>
> Il 07/04/21 20:19, abhin...@codeaurora.org ha scritto:
> > Hi Marijn
> >
> > On 2021-04-06 14:47, Marijn Suijten wrote:
> >> Leaving this at a close-to-maximum register value 0xFFF0 means it takes
> >> very long for the MDSS to
On Thu, Apr 8, 2021 at 4:16 PM AngeloGioacchino Del Regno
wrote:
>
>
> Il gio 8 apr 2021, 21:05 Rob Clark ha scritto:
>>
>> On Wed, Apr 7, 2021 at 12:11 PM AngeloGioacchino Del Regno
>> wrote:
>> >
>> > Il 07/04/21 20:19, abhin...@codeaurora.org
On Thu, Apr 8, 2021 at 7:28 PM Abhinav Kumar wrote:
>
> Add the dpu_dbg module which adds supports to dump dpu registers
> which can be used in case of error conditions.
>
> changes in v3:
> - Get rid of registration mechanism for sub-modules and instead get
>this information from the dpu cat
GHT to double the vtotal
drm/msm/mdp5: Do not multiply vclk line count by 100
Rob Clark (18):
drm/msm: Ratelimit invalid-fence message
drm/msm: Fix a5xx/a6xx timestamps
Merge tag 'drm-msm-fixes-2021-04-02' into msm-next
drm/msm: Remove unused freed llist node
On Mon, Apr 12, 2021 at 7:28 AM Daniel Vetter wrote:
>
> On Thu, Apr 08, 2021 at 08:23:42AM -0700, Rob Clark wrote:
> > On Thu, Apr 8, 2021 at 4:15 AM Daniel Vetter wrote:
> > >
> > > On Mon, Apr 05, 2021 at 10:45:23AM -0700, Rob Clark wrote:
> > > >
fset += MSM_DP_CONTROLLER_AUX_OFFSET;
> > diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h
> > b/drivers/gpu/drm/msm/dp/dp_catalog.h
> > index 176a902..e7e8b13 100644
> > --- a/drivers/gpu/drm/msm/dp/dp_catalog.h
> > +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
>
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