On Mon, 2017-02-20 at 14:30 +0100, Philipp Zabel wrote:
> Use drm_plane_helper_check_state to clip raw user coordinates to crtc
> bounds. This checks for full plane coverage and scaling already, so
> we can drop some custom checks. Use the clipped coordinates everywhere.
>
> Sugg
On Fri, 2017-02-17 at 19:28 +0100, Lucas Stach wrote:
> The Prefetch Resolve Engine is a prefetch and tile resolve engine
> which prefetches display data from DRAM to an internal SRAM region.
> It has a single clock for configuration register access and the
> functional units. A single shared inter
On Fri, 2017-02-17 at 19:28 +0100, Lucas Stach wrote:
> This adds support for the i.MX6 QuadPlus PRE units. Currently only
> linear prefetch into SRAM is supported, other modes of operation
> like the tiled-to-linear conversion will be added later.
>
> Signed-off-by: Lucas Stach
> ---
> drivers/
On Fri, 2017-02-17 at 19:28 +0100, Lucas Stach wrote:
> This adds support for the i.MX6 QUadPlus PRG unit. It glues together the
> IPU and the PRE units.
>
> Signed-off-by: Lucas Stach
> ---
> drivers/gpu/ipu-v3/Makefile | 2 +-
> drivers/gpu/ipu-v3/ipu-prg.c | 413
>
Hi Dan,
On Sat, 2017-02-11 at 21:09 +, Dan MacDonald wrote:
> Hi Phillipp
>
> I'm having trouble getting xf86-video-armada working properly on a
> Element 14 / Embest SABRE Lite board running Arch Linux with kernel
> 4.9.8. I have been in touch with RMK and he's confident the crash
> below is
Previously, the overlay plane position would only be updated when the
plane was first enabled or during a modeset. We can instruct the DP to
move the plane also when just updating the EBA.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/imx/ipuv3-plane.c | 8 +---
1 file changed, 5
Otherwise, if the image base address is kept at zero, and if the user
ignores the error return value, the IPU may be configured to write into
the dma-apbh@0011 region for large frames, which will lock up the
system.
Reported-by: Russell King
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu
The IPU does not natively understand bayer formats, but it can pass them
through unchanged. Add support for setting the image base address and
cropping offset to ipu_cpmem_set_image.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-cpmem.c | 13 +
1 file changed, 13
-by: Philipp Zabel
---
drivers/gpu/drm/imx/ipuv3-plane.c | 2 +-
drivers/gpu/ipu-v3/ipu-common.c | 8 +---
drivers/gpu/ipu-v3/ipu-dp.c | 12 ++--
drivers/gpu/ipu-v3/ipu-prv.h | 7 ++-
include/video/imx-ipu-v3.h| 2 +-
5 files changed, 19 insertions(+), 12
From: Lucas Stach
This has never worked properly, as the IRQ got retriggered immediately
on unmask. Remove the IRQ wait dance, as it is apparently safe to disable
the DC channel at any point in time.
Signed-off-by: Lucas Stach
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-dc.c | 61
should report commit_hw_done only after wait_for_vblanks.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/imx/imx-drm-core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/imx/imx-drm-core.c
b/drivers/gpu/drm/imx/imx-drm-core.c
index f562cb7964b08
h (1):
gpu: ipu-v3: remove IRQ dance on DC channel disable
Philipp Zabel (3):
gpu: ipu-v3: add unsynchronised DP channel disabling
drm/imx: call drm_atomic_helper_commit_hw_done after
drm_atomic_helper_wait_for_vblanks
drm/imx: add deferred plane disabling
drivers/gpu/drm/imx
ny waiting whatsoever. The imx_drm_atomic_commit_tail then
calls a new ipu_plane_disable_deferred function that does the actual
IDMAC teardown of the planes that are flagged for deferred disabling.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/imx/imx-drm-core.c | 7 +++
drivers/gpu/drm/imx/ip
On Mon, 2017-02-27 at 12:33 +0100, Lucas Stach wrote:
> Am Montag, den 27.02.2017, 12:28 +0100 schrieb Philipp Zabel:
> > When disabling the foreground DP channel during a modeset, the DC is
> > already disabled without waiting for end of frame. There is no reason
> > to wait
transparent bursts.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/imx/ipuv3-plane.c | 97 ++-
drivers/gpu/drm/imx/ipuv3-plane.h | 1 +
2 files changed, 97 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c
b/drivers/gpu/drm/imx/ipuv3
Some hardware can read the alpha components separately and then
conditionally fetch color components only for non-zero alpha values.
This patch adds fourcc definitions for two-plane RGB formats with an
8-bit alpha channel on a second plane.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm
: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-common.c | 6 +
drivers/gpu/ipu-v3/ipu-cpmem.c | 57 +
include/video/imx-ipu-v3.h | 22
3 files changed, 85 insertions(+)
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3
Allow to calculate EBA for planes other than plane 0. This is in
preparation for the following patch, which adds support for separate
alpha planes.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/imx/ipuv3-plane.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff
Hi Dan,
On Mon, 2017-02-27 at 11:43 +, Dan MacDonald wrote:
> Hi Phillipp
>
> It sounds like you need me to test a new kernel build with these patches now?
if you could find the time, that would be helpful.
> I'm new round here so could you please give me the git commands to
> check out you
-by: Philipp Zabel
---
Changes since v1:
- Only clear the DP_S_SRM_MODE bitfield in the IPU_SRM_PRI2 register, not
everything else.
---
drivers/gpu/drm/imx/ipuv3-plane.c | 2 +-
drivers/gpu/ipu-v3/ipu-common.c | 8 +---
drivers/gpu/ipu-v3/ipu-dp.c | 12 ++--
drivers/gpu/ipu
From: Lucas Stach
This has never worked properly, as the IRQ got retriggered immediately
on unmask. Remove the IRQ wait dance, as it is apparently safe to disable
the DC channel at any point in time.
Signed-off-by: Lucas Stach
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-dc.c | 61
should report commit_hw_done only after wait_for_vblanks.
Signed-off-by: Philipp Zabel
Reviewed-by: Lucas Stach
---
drivers/gpu/drm/imx/imx-drm-core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/imx/imx-drm-core.c
b/drivers/gpu/drm/imx/imx-drm-core.c
index
t sure if this
fixes the issue above, too.
regards
Philipp
Lucas Stach (1):
gpu: ipu-v3: remove IRQ dance on DC channel disable
Philipp Zabel (3):
gpu: ipu-v3: add unsynchronised DP channel disabling
drm/imx: call drm_atomic_helper_commit_hw_done after
drm_atomic_helper_wait_for_vb
ny waiting whatsoever. The imx_drm_atomic_commit_tail then
calls a new ipu_plane_disable_deferred function that does the actual
IDMAC teardown of the planes that are flagged for deferred disabling.
Signed-off-by: Philipp Zabel
Reviewed-by: Lucas Stach
---
drivers/gpu/drm/imx/imx-drm-core.c | 7 ++
On Mon, 2017-02-27 at 17:23 +0100, Daniel Vetter wrote:
> On Mon, Feb 27, 2017 at 12:52:46PM +0100, Philipp Zabel wrote:
> > Some hardware can read the alpha components separately and then
> > conditionally fetch color components only for non-zero alpha values.
> > T
On Mon, 2017-02-27 at 17:25 +0100, Daniel Vetter wrote:
> On Mon, Feb 27, 2017 at 02:14:57PM +0100, Philipp Zabel wrote:
> > Disabling planes will consist of two steps as of the following patch.
> > First, the DP is asked to stop at the next vblank, and then, after the
> >
Hi Christophe,
Am Montag, den 31.10.2016, 18:59 +0100 schrieb Christophe JAILLET:
> 'drm_dev_alloc()' returns an error pointer in case of error, not NULL
> So test it with IS_ERR.
>
> This behavior has been introduced recently in 0f2886057be3. For some
> reason, this file has not been updated.
>
Hi Dave,
Am Montag, den 24.10.2016, 16:52 +0200 schrieb Philipp Zabel:
> Hi Dave,
>
> please consider merging this tag containing a few fixes for the recently
> merged active plane reconfiguration support, a label hidden to remove a
> build warning, a fixed error path, and fixes
DP++ -> Video output
>
> Cc: Martyn Welch
> Cc: Martin Donnelly
> Cc: Daniel Vetter
> Cc: Enric Balletbo i Serra
> Cc: Philipp Zabel
> Cc: Rob Herring
> Cc: Fabio Estevam
> CC: David Airlie
> CC: Thierry Reding
> CC: Thierry Reding
> CC: Archit Taneja
>
Am Montag, den 07.11.2016, 14:17 +0100 schrieb Thierry Reding:
> On Mon, Nov 07, 2016 at 06:12:43PM +0800, Chen-Yu Tsai wrote:
> > On Sun, Nov 6, 2016 at 7:09 PM, Icenowy Zheng wrote:
> > > The enable gpio of simple-panel may be used by a simplefb or other
> > > driver on the panel's display befor
Am Montag, den 07.11.2016, 19:03 +0900 schrieb Gustavo Padovan:
> From: Gustavo Padovan
>
> drm_atomic_set_fence_for_plane() is smart and won't overwrite
> plane_state->fence if the user already set an explicit fence there.
>
> Cc: Philipp Zabel
> Signed-off-by: G
Am Dienstag, den 08.11.2016, 17:04 +0100 schrieb Lucas Stach:
> If the DC clock is disabled before the attached IDMACs are properly
> stopped the IDMACs may hang the IPU or even the whole system.
>
> Make sure the IDMACs are in safe state by disabling the planes before
> removal of the DC clock.
Am Dienstag, den 08.11.2016, 16:57 +0100 schrieb Lucas Stach:
> Adapting the videomode to the hardware constraints is something that
> can and must happen during normal operation and isn't something that
> the user can avoid. So printing a warning each time it happens isn't
> helpful.
>
> Demote t
Hi Dave,
this tag contains a single patch to fix a regression introduced by the
atomic modeset conversion, with can occasionally hang the system during
crtc atomic_disable by disabling the display controller module and plane
IDMAC channels in the wrong order.
regards
Philipp
The following change
Lucas Stach (1):
gpu: ipu-di: silence videomode logspam
Philipp Zabel (9):
drm/imx: ipuv3-plane: request modeset if plane offsets changed
drm/imx: ipuv3-plane: merge ipu_plane_atomic_set_base into atomic_update
drm/imx: ipuv3-plane: let
>
> Cc: CK Hu
> Cc: Philipp Zabel
> Signed-off-by: Daniel Vetter
Acked-by: Philipp Zabel
regards
Philipp
> ---
> drivers/gpu/drm/drm_irq.c | 37
> +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +-
> 2 files
,
> + HDMI_NEW_EDID,
> + HDMI_NEW_ELD,
> +};
> +
> +struct device;
> +
> +struct hdmi_notifier {
> + struct mutex lock;
> + struct list_head head;
> + struct kref kref;
> + struct blocking_notifier_head notifiers;
> + struct device *dev;
Issue hot-plug detection, EDID update, and ELD update notifications
from the CEC and HDMI drivers using the HDMI state notifier support.
Signed-off-by: Philipp Zabel
---
This patch depends on the "video: add HDMI state notifier support" patch [1] by
Hans Verkuil, based on Russell King
Hi Laurent,
Am Donnerstag, den 24.11.2016, 23:16 +0200 schrieb Laurent Pinchart:
> Hi Andy,
>
> As the author of the DW-HDMI DT bindings this question is addressed to you,
> but information from anyone is more than welcome.
>
> The DT bindings specify two clocks named "iahb" and "isfr" but don'
Am Freitag, den 25.11.2016, 17:45 +0200 schrieb Laurent Pinchart:
> Hi Philipp,
>
> On Friday 25 Nov 2016 10:56:55 Philipp Zabel wrote:
> > Am Donnerstag, den 24.11.2016, 23:16 +0200 schrieb Laurent Pinchart:
> > > Hi Andy,
> > >
> > > As the author o
Hi Christopher,
Am Dienstag, den 29.11.2016, 16:45 +0100 schrieb Christopher Spinrath:
> Hi all,
>
> I am trying to enable the second display pipeline of my imx6q based
> Utilite Pro. I appended a devicetree patch to this email for reference.
>
> While it works perfectly on its own there occur k
-ENODEV return code.
Reported-by: Nikita Yushchenko
Fixes: ebc944613567 ("drm: convert drivers to use drm_of_find_panel_or_bridge")
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/imx/parallel-display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/g
mic_flush = mtk_drm_crtc_atomic_flush,
> .atomic_enable = mtk_drm_crtc_atomic_enable,
> + .atomic_disable = mtk_drm_crtc_atomic_disable,
> };
>
> static int mtk_drm_crtc_init(struct drm_device *drm,
For mediatek,
Acked-by: Philipp Zabel
regards
Philipp
k_drm_crtc_atomic_begin,
> .atomic_flush = mtk_drm_crtc_atomic_flush,
> + .atomic_enable = mtk_drm_crtc_atomic_enable,
> };
>
> static int mtk_drm_crtc_init(struct drm_device *drm,
For imx-drm and mediatek,
Acked-by: Philipp Zabel
regards
Philipp
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
On Wed, 2017-06-28 at 12:31 +0300, Laurentiu Palcu wrote:
> The BGRA appears twice in the ipu_plane_formats[] list. The
> duplicate should be BGRX.
>
> The original commit is:
>
> commit 59d6b7189a96 ("drm/imx: ipuv3-plane: enable support for RGBX
> and RGBA pixel formats")
>
> S
On Wed, 2017-07-12 at 10:13 +0200, Maarten Lankhorst wrote:
> for_each_obj_in_state is about to be removed, so use the new atomic
> iterator macros.
>
> Signed-off-by: Maarten Lankhorst
> Cc: Philipp Zabel
> ---
> drivers/gpu/drm/imx/imx-drm-core.c | 8
> d
On Tue, 2017-07-11 at 16:33 +0200, Maarten Lankhorst wrote:
> drm_atomic_helper_swap_state() will be changed to interruptible waiting
> in the next few commits, so all drivers have to be changed to handling
> failure.
>
> Signed-off-by: Maarten Lankhorst
> Cc: CK Hu
> Cc
On Wed, 2017-07-12 at 10:13 +0200, Maarten Lankhorst wrote:
> for_each_obj_in_state is about to be removed, so use the new atomic
> iterator macros.
>
> Signed-off-by: Maarten Lankhorst
> Cc: CK Hu
> Cc: Philipp Zabel
> Cc: Matthias Brugger
> Cc: linux-arm-ker...@
On Tue, 2017-02-28 at 12:45 +0100, Daniel Vetter wrote:
> On Tue, Feb 28, 2017 at 10:59:54AM +0100, Philipp Zabel wrote:
> > On Mon, 2017-02-27 at 17:25 +0100, Daniel Vetter wrote:
> > > On Mon, Feb 27, 2017 at 02:14:57PM +0100, Philipp Zabel wrote:
> > > > Disabl
Allow to calculate EBA for planes other than plane 0. This is in
preparation for the following patch, which adds support for separate
alpha planes.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/imx/ipuv3-plane.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff
: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-common.c | 6 +
drivers/gpu/ipu-v3/ipu-cpmem.c | 57 +
include/video/imx-ipu-v3.h | 22
3 files changed, 85 insertions(+)
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3
Some hardware can read the alpha components separately and then
conditionally fetch color components only for non-zero alpha values.
This patch adds fourcc definitions for two-plane RGB formats with an
8-bit alpha channel on a second plane.
Signed-off-by: Philipp Zabel
---
Changes since v1
transparent bursts.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/imx/ipuv3-plane.c | 97 ++-
drivers/gpu/drm/imx/ipuv3-plane.h | 1 +
2 files changed, 97 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c
b/drivers/gpu/drm/imx/ipuv3
ne without any waiting whatsoever. The imx_drm_atomic_commit_tail then
calls a new ipu_plane_disable_deferred function that does the actual
IDMAC teardown of the planes that are flagged for deferred disabling,
after waiting for the vblank.
Signed-off-by: Philipp Zabel
---
Changes since v2:
- A
-by: Philipp Zabel
Reviewed-by: Lucas Stach
---
drivers/gpu/drm/imx/ipuv3-plane.c | 2 +-
drivers/gpu/ipu-v3/ipu-common.c | 8 +---
drivers/gpu/ipu-v3/ipu-dp.c | 12 ++--
drivers/gpu/ipu-v3/ipu-prv.h | 7 ++-
include/video/imx-ipu-v3.h| 2 +-
5 files changed
nce on DC channel disable
Philipp Zabel (3):
gpu: ipu-v3: add unsynchronised DP channel disabling
drm/imx: don't wait for vblank and stop calling cleanup_planes in
commit_tail
drm/imx: add deferred plane disabling
drivers/gpu/drm/imx/imx-drm-core.c | 20 +++--
drivers/g
drm_atomic_helper_cleanup_planes only calls the cleanup_fb plane
helpers, which we don't implement as a CMA framebuffer based driver.
There is no reason to wait for vblanks in commit_tail only to do nothing
afterwards.
Signed-off-by: Philipp Zabel
---
Changes since v2:
- New patch that re
From: Lucas Stach
This has never worked properly, as the IRQ got retriggered immediately
on unmask. Remove the IRQ wait dance, as it is apparently safe to disable
the DC channel at any point in time.
Signed-off-by: Lucas Stach
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-dc.c | 61
transparent bursts.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/imx/ipuv3-plane.c | 97 ++-
drivers/gpu/drm/imx/ipuv3-plane.h | 1 +
2 files changed, 97 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c
b/drivers/gpu/drm/imx/ipuv3
Allow to calculate EBA for planes other than plane 0. This is in
preparation for the following patch, which adds support for separate
alpha planes.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/imx/ipuv3-plane.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff
Some hardware can read the alpha components separately and then
conditionally fetch color components only for non-zero alpha values.
This patch adds fourcc definitions for two-plane RGB formats with an
8-bit alpha channel on a second plane.
Signed-off-by: Philipp Zabel
---
Changes since v2
: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-common.c | 6 +
drivers/gpu/ipu-v3/ipu-cpmem.c | 57 +
include/video/imx-ipu-v3.h | 22
3 files changed, 85 insertions(+)
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3
On Tue, 2017-02-28 at 18:58 +0200, Ville Syrjälä wrote:
> On Tue, Feb 28, 2017 at 03:12:35PM +0100, Philipp Zabel wrote:
> > Some hardware can read the alpha components separately and then
> > conditionally fetch color components only for non-zero alpha values.
> > T
//git.pengutronix.de/git/pza/linux.git tags/v4.10-ipu-dp-plane-fix
Does the error persist? Could you try git:// instead of https://?
regards
Philipp
> Thanks
>
> On Mon, Feb 27, 2017 at 1:13 PM, Philipp Zabel wrote:
> > Hi Dan,
> >
> > On Mon, 2017-02-27 at 11:43 +00
On Fri, 2017-03-03 at 19:25 +0100, Lucas Stach wrote:
[...]
> > > +int ipu_pre_get(struct ipu_pre *pre)
> > > +{
> > > + u32 val;
> > > +
> > > + if (pre->in_use)
> > > + return -EBUSY;
> >
> > This could race for in_use ...
>
> All the PRE/PRG configuration functions are thread unsafe, w
On Mon, 2017-03-06 at 09:55 +, Dan MacDonald wrote:
> Hi Phillipp
>
> I've just tried those commands on my work machine where we allow
> (need) git access and I get the same errors as I did at home.
>
> Thanks
>
> On Mon, Mar 6, 2017 at 8:39 AM, Philipp Zabel
[2].
[1] https://git-scm.com/book/en/v2
[2] https://git-scm.com/book/en/v2/Git-Branching-Branches-in-a-Nutshell
regards
Philipp
> Thanks
>
> On Mon, Mar 6, 2017 at 1:50 PM, Philipp Zabel wrote:
> > On Mon, 2017-03-06 at 09:55 +, Dan MacDonald wrote:
> >> Hi Phillipp
&g
t of the struct.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/etnaviv/Kconfig | 1 +
drivers/gpu/drm/etnaviv/etnaviv_gem.h| 1 +
drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 34 +++-
drivers/gpu/drm/etnaviv/etnaviv_gpu.c| 5 +++-
The next patch will need the dma_fence to create the sync_file in
etnaviv_ioctl_gem_submit, in case an out_fence_fd is requested.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/etnaviv/etnaviv_gem.h| 3 ++-
drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 8 +++-
drivers/gpu/drm
Based on commit 4cd0945901a6 ("drm/msm: submit support for out-fences").
We increment the minor driver version so userspace can detect explicit
fence support.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/etnaviv/etnaviv_drv.c| 2 +-
drivers/gpu/drm/etnaviv/etnaviv_gem_sub
Hi Gustavo,
thank you for the review.
On Wed, 2017-03-08 at 11:37 -0300, Gustavo Padovan wrote:
[...]
> > @@ -385,6 +396,25 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev,
> > void *data,
> > goto err_submit_objects;
> > }
> >
> > + if (args->flags & ETNA_SUBMIT_FENCE
On Wed, 2017-03-08 at 11:48 -0300, Gustavo Padovan wrote:
[...]
> > @@ -437,10 +447,25 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev,
> > void *data,
> > goto out;
> > }
> >
> > + if (args->flags & ETNA_SUBMIT_FENCE_FD_OUT) {
> > + sync_file = sync_file_creat
On Wed, 2017-03-08 at 11:42 -0300, Gustavo Padovan wrote:
> Hi Philipp,
>
> 2017-03-08 Philipp Zabel :
>
> > The next patch will need the dma_fence to create the sync_file in
> > etnaviv_ioctl_gem_submit, in case an out_fence_fd is requested.
> >
&g
Hi Dan,
On Fri, 2017-03-10 at 11:11 +, Dan MacDonald wrote:
> Should your patches work fine under 4.11-rc1 Phillipp or do I need to
> test againt the very latest git? I realise that would be preferred.
The patches from the v4.10-ipu-dp-plane-fix-2 tag should work under
v4.11-rc1, they are app
On Wed, 2017-03-08 at 12:13 +0100, Lucas Stach wrote:
> The Prefetch Resolve Engine is a prefetch and tile resolve engine
> which prefetches display data from DRAM to an internal SRAM region.
> It has a single clock for configuration register access and the
> functional units. A single shared inter
From: Lucas Stach
The i.MX6 QuadPlus IPU needs to PRG unit to gain access to the
data bus. Make sure it is present and available to be used.
Signed-off-by: Lucas Stach
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-common.c | 11 ++-
drivers/gpu/ipu-v3/ipu-prv.h| 1 +
2
From: Lucas Stach
This adds support for the i.MX6 QUadPlus PRG unit. It glues together the
IPU and the PRE units.
Signed-off-by: Lucas Stach
Signed-off-by: Philipp Zabel
---
v3: Fix modular build (drop duplicate module_platform_driver, export symbols)
---
drivers/gpu/ipu-v3/Makefile
From: Lucas Stach
This adds support for the i.MX6 QuadPlus PRE units. Currently only
linear prefetch into SRAM is supported, other modes of operation
like the tiled-to-linear conversion will be added later.
Signed-off-by: Lucas Stach
Signed-off-by: Philipp Zabel
---
v3: Fix modular build
From: Lucas Stach
On i.MX6 QuadPlus the PRG needs to be clocked in order to pass
through the data access requests from the IDMAC. This call is a
no-op for other all other SoCs.
Signed-off-by: Lucas Stach
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/imx/ipuv3-crtc.c | 2 ++
1 file changed
signaling.
The only external dependency is the SRAM region to use for the
prefetch double buffer.
Signed-off-by: Lucas Stach
Signed-off-by: Philipp Zabel
---
.../bindings/display/imx/fsl-imx-drm.txt | 26 ++
1 file changed, 26 insertions(+)
diff --git a/Documentation
From: Lucas Stach
Document the valid compatible strings for the IPUv3.
On i.MX6 QuadPlus the IPU needs to know which PRG has to be
used for this IPU instance. Add a "fsl,prg" property containing
a phandle pointing to the correct PRG device.
Signed-off-by: Lucas Stach
Signed-off-b
From: Lucas Stach
Using non-zero AXI IDs for anything other than the display channels
collides with the PRG AXI snooping, so only do this if there is no
PRG present.
Signed-off-by: Lucas Stach
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 7 ++-
1 file changed
more work, but it already wires up the basic interaction between
imx-drm, the IPUv3 driver and the PRG and PRE drivers.
Signed-off-by: Lucas Stach
Signed-off-by: Philipp Zabel
---
v3: Fix modular build (export ipu_planes_assign_pre symbol)
---
drivers/gpu/drm/imx/imx-drm-core.c | 5
connections need to be described in the DT, as the PRE<->PRG
assignment is a mix between fixed and muxable connections.
Signed-off-by: Lucas Stach
Acked-by: Rob Herring
Signed-off-by: Philipp Zabel
---
.../bindings/display/imx/fsl-imx-drm.txt | 25 ++
On Wed, 2017-03-15 at 14:52 +0800, Liu Ying wrote:
> No one is using the structure imx_drm_component, so let's remove the
> definition to save several lines.
>
> Signed-off-by: Liu Ying
Thanks, applied to imx-drm/next.
regards
Philipp
> ---
> drivers/gpu/drm/imx/imx-drm-core.c | 5 -
> 1
Hi Gustavo,
On Mon, 2017-03-13 at 14:37 -0300, Gustavo Padovan wrote:
[...]
> I was thinking on some function that would iterate over all fences in
> the fence_array and check their context. The if we find our own gpu
> context in there we fail the submit.
Why would we have to fail if somebody fe
drm/imx: enable/disable PRG on CRTC enable/disable
drm/imx: use PRG/PRE when possible
Philipp Zabel (11):
drm/imx: ipuv3-plane: use drm_plane_helper_check_state, clipped
coordinates
drm/imx: ipuv3-plane: update overlay plane position also without modeset
gpu: ipu-cpmem: set
On Fri, 2017-03-17 at 11:00 -0300, Gustavo Padovan wrote:
> 2017-03-16 Philipp Zabel :
>
> > Hi Gustavo,
> >
> > On Mon, 2017-03-13 at 14:37 -0300, Gustavo Padovan wrote:
> > [...]
> > > I was thinking on some function that would iterate over all fences i
On Fri, 2017-03-17 at 10:55 -0300, Gustavo Padovan wrote:
> 2017-03-16 Rob Clark :
>
> > On Wed, Mar 8, 2017 at 9:37 AM, Gustavo Padovan wrote:
> > >> diff --git a/include/uapi/drm/etnaviv_drm.h
> > >> b/include/uapi/drm/etnaviv_drm.h
> > >> index 2584c1cca42f6..e9c388a1d8ebe 100644
> > >> --- a
The next patch will need the dma_fence to create the sync_file in
etnaviv_ioctl_gem_submit, in case an out_fence_fd is requested.
Signed-off-by: Philipp Zabel
Reviewed-by: Gustavo Padovan
---
drivers/gpu/drm/etnaviv/etnaviv_gem.h| 3 ++-
drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
Add a helper to check if all fences in a fence array are from a given
context. For convenience, the function can also handle being given a
non-array fence.
Signed-off-by: Philipp Zabel
---
drivers/dma-buf/dma-fence-array.c | 26 ++
include/linux/dma-fence-array.h | 2
Based on commit 4cd0945901a6 ("drm/msm: submit support for out-fences").
We increment the minor driver version so userspace can detect explicit
fence support.
Signed-off-by: Philipp Zabel
Reviewed-by: Gustavo Padovan
---
v2: Dropped unnecessary braces
---
drivers/gpu/drm/etnaviv/etn
t of the struct.
Signed-off-by: Philipp Zabel
---
v2: Use dma_fence_match_context to skip waiting if all in-fences are ours.
---
drivers/gpu/drm/etnaviv/Kconfig | 1 +
drivers/gpu/drm/etnaviv/etnaviv_gem.h| 1 +
drivers/gpu/drm/etnaviv/etnaviv_ge
Use platform_register_drivers instead of open coding the iteration over
component platform drivers in the mtk_drm_drv and mtk_hdmi modules.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 27 ---
drivers/gpu/drm/mediatek/mtk_hdmi.c| 27
Use platform_register_drivers instead of open coding the iteration over
component platform drivers in the vc4_drv module.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/vc4/vc4_drv.c | 22 --
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm
Use the dma_fence_match_context helper to check if all backing fences
are from our own context, in which case we don't have to wait.
Signed-off-by: Philipp Zabel
Cc: Rob Clark
Cc: Gustavo Padovan
---
Not sure if this can be handled exactly the same as for etnaviv. This depends on
d5b72a2
On Sun, 2017-03-19 at 11:28 +, Emil Velikov wrote:
> Hi Philipp,
>
> I think you patch is OK, just a small question about the existing code.
> It might be better suited for Eric... not sure.
>
> On 17 March 2017 at 17:00, Philipp Zabel wrote:
> > Use platform_reg
On Sat, 2017-03-18 at 08:48 -0400, Rob Clark wrote:
> On Fri, Mar 17, 2017 at 2:38 PM, Philipp Zabel wrote:
> > Use the dma_fence_match_context helper to check if all backing fences
> > are from our own context, in which case we don't have to wait.
> >
> > Sign
Hi Martyn,
On Tue, 2017-03-21 at 09:50 +, Martyn Welch wrote:
> I have an i.MX6 platform with 2 display port interfaces, one driven by the
> HDMI interface, the other by LVDS, both via bridges. We are currently
> experiencing the following error when we boot with the monitor connected
> to the
On Tue, 2017-03-21 at 16:12 +0100, Neil Armstrong wrote:
> Some display pipelines can only provide non-RBG input pixels to the HDMI TX
> Controller, this patch takes the pixel format from the plat_data if provided.
>
> Signed-off-by: Neil Armstrong
On i.MX6 we could provide RGB/YUV bus formats d
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