[PATCH] drm/edid: Fix EDID Established Timings I and II

thus brings them into line with the identical timings in drm_dmt_modes[]. Signed-off-by: Paul Parsons --- diff -ru a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c --- a/drivers/gpu/drm/drm_edid.c2016-03-14 04:28:54.0 + +++ b/drivers/gpu/drm/drm_edid.c2016-04

[PATCH RFC] drm/radeon: Fix PCIe lane width calculation

ced. Hence submitting this as an RFC. Signed-off-by: Paul Parsons --- diff -ru a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c --- a/drivers/gpu/drm/radeon/si_dpm.c 2016-03-14 04:28:54.0 + +++ b/drivers/gpu/drm/radeon/si_dpm.c 2016-04-02 11:43:47.146616182 +0100

[PATCH] drm/edid: Fix DMT 1024x768@43Hz (interlaced) timings

One of the VESA DMT timings in drm_dmt_modes[] is slightly off. 1024x768 at 43Hz (interlaced) vsync_end should be 776, not 772. This brings it into line with the identical timings in edid_est_modes[]. Signed-off-by: Paul Parsons --- diff -ru a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm

[PATCH] drm/edid: Fix parsing of EDID 1.4 Established Timings III descriptor

The EDID 1.4 specification section 3.10.3.9 defines an Established Timings III descriptor (tag #F7h). The parsing of this descriptor by drm_est3_modes() is off by one byte: the offset of the first timing bitmap is 6, not 5. Signed-off-by: Paul Parsons --- diff -ru a/drivers/gpu/drm/drm_edid.c b

[PATCH] drm/edid: Fix parsing of EDID 1.4 Established Timings III descriptor

The EDID 1.4 specification section 3.10.3.9 defines an Established Timings III descriptor (tag #F7h). The parsing of this descriptor by drm_est3_modes() is off by one byte: the offset of the first timing bitmap is 6, not 5. Signed-off-by: Paul Parsons --- diff -ru a/drivers/gpu/drm/drm_edid.c b