Acked-by: Michal Mrozek
-Original Message-
From: Harrison, John C
Sent: Thursday, March 3, 2022 11:38 PM
To: intel-...@lists.freedesktop.org
Cc: DRI-Devel@Lists.FreeDesktop.Org; Harrison, John C
; Ceraolo Spurio, Daniele
; Mrozek, Michal
Subject: [PATCH v3 4/4] drm/i915: Improve
Commit 9bb66c179f50 ("drm/i915: Reserve some kernel space per
vm") has reserved an object for kernel space usage.
Userspace, though, needs to know the full address range.
Fixes: 9bb66c179f50 ("drm/i915: Reserve some kernel space per vm")
Signed-off-by: Andi Shyti
Cc: Andrzej Hajda
Cc: Chris Wil
> > Lionel, Michal, thoughts?
Compute UMD needs to know exact GTT total size.
> If we provide the total GTT size we will have one page that will be contended
> between kernel and userspace and, if userspace is unaware that the page
> belongs to the > kernel, we might step on each other toe.
That's fine, Compute needs to know total GTT size.
Not available GTT size.
On Wed, Mar 13, 2024 at 09:19:48PM +0100, Andi Shyti wrote:
> Hi,
>
> this series does basically two things:
>
> 1. Disables automatic load balancing as adviced by the hardware
>workaround.
>
> 2. Assigns all the CCS slices to one single user engine. The user
>will then be able to query
The caching mode for buffer objects with VRAM as a possible placement was
forced to write-combined, regardless of placement.
However, write-combined system memory is expensive to allocate and even though
it is pooled, the pool is expensive to shrink, since it involves global CPU TLB
flushes.
M
Commit 9bb66c179f50 ("drm/i915: Reserve some kernel space per
vm") reduces the available VM space of one page in order to apply
Wa_16018031267 and Wa_16018063123.
This page was reserved indiscrimitely in all platforms even when not needed.
Limit it to DG2 onwards.
Fixes: 9bb66c179f50 ("drm/i915:
"Adding Michal from the compute userspace team for sharing references to the
code.
Quoting Christian König (2024-11-19 12:00:44)
> Am 19.11.24 um 00:37 schrieb Matthew Brost:
> > From: Tejas Upadhyay
> >
> > In order to avoid having userspace to use MI_MEM_FENCE, we are
> > adding a mechanism f
>>Allow user to provide a low latency hint per exec queue. When set, KMD sends
>>a hint to GuC which results in special handling for this exec queue. SLPC
>>will ramp the GT frequency aggressively every time it switches to this exec
>>queue.
>>
>>We need to enable the use of SLPC Compute strateg
Acked-by: Michal Mrozek
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