On 12/04/2021 17:29, Jassi Brar wrote:
> On Mon, Apr 12, 2021 at 6:18 AM Yongqiang Niu
> wrote:
>>
>> This series base linux 5.12-rc2
>> these patches will cause home ui flick when cursor moved,
>> there is no fix solution yet, revert these patches first.
>>
>> change since v1:
>> add mtk-gce.t
Hi Jason,
On 05/08/2021 22:52, jason-jh.lin wrote:
> Add mt8195 vdosys0 clock driver name and routing table to
> the driver data of mtk-mmsys.
>
I'd like to see the implementation of vdosys1 as well, to better understand why
we need two compatibles.
> Signed-off-by: jason-jh.lin
> ---
> This p
On 28/07/2021 07:34, Nancy.Lin wrote:
> Hi Enric,
>
> Thanks for your review.
>
> On Fri, 2021-07-23 at 13:05 +0200, Enric Balletbo Serra wrote:
>> Hi Nancy,
>>
>> Thank you for your patch.
>>
>> Missatge de Nancy.Lin del dia dj., 22 de
>> jul.
>> 2021 a les 11:45:
>>>
>>> Add mt8195 vdosys1
On 22/07/2021 11:45, Nancy.Lin wrote:
> Add mmsys config API.
This patch is doing a lot of things, it adds a "config" and it adds cmdq
support. Please explain better in the commit message what the config is for.
Please add comments to the different values of struct mtk_mmsys_config.
I understa
ard description, also is not needed on all of them, the reset is optional,
> so the change is compatible with all boards.
>
> Cc: Jitao Shi
> Suggested-by: Chun-Kuang Hu
> Signed-off-by: Enric Balletbo i Serra
Reviewed-by: Matthias Brugger
> ---
>
> (no changes s
On 27/10/2020 17:08, Fabien Parent wrote:
> Hi Chun-Kuang,
>
> On Fri, Oct 23, 2020 at 5:52 PM Chun-Kuang Hu wrote:
>>
>> Hi, Fabien:
>>
>> Fabien Parent 於 2020年10月23日 週五 下午9:31寫道：
>>>
>>> Add the main (DSI) drm display path for MT8167.
>>>
>>> Signed-off-by: Fabien Parent
>>> ---
>>>
>>> Ch
On 02/08/2021 10:59, Yongqiang Niu wrote:
> base v5.14-rc1
>
> Yongqiang Niu (2):
> soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4
> soc: mediatek: mmsys: Add mt8192 mmsys routing table
>
Series queued in v5.15-tmp/soc
Thanks
> drivers/soc/mediatek/mt8192-mmsys.h| 67
>
On 04/08/2021 09:30, Frank Wunderlich wrote:
> Hi
>
> can you please test if your device still work after applying this
>
> https://patchwork.kernel.org/project/linux-mediatek/patch/20210729070549.5514-1-li...@fw-web.de/
>
> and
>
> duplicate value constants in your routes?
>
> e.g. changin
On 29/01/2021 10:22, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add mtk mutex support for MT8183 SoC.
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> Reviewed-by: CK Hu
> ---
> drivers/soc/mediatek/mtk-mutex.c | 50
> 1 file changed, 50
On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
> move register operation into mmsys path select function
Why do you want to do that. It seems the register access pattern is the
same for all SoCs so far supported, so I don't see the need to duplicate
the code in every SoC.
Regards,
On Thu, Jan 21, 2021 at 07:46:44AM +0800, Chun-Kuang Hu wrote:
> Hi, Matthias:
>
> Matthias Brugger 於 2021年1月21日 週四 上午2:27寫道：
> >
> > On Thu, Jan 07, 2021 at 07:17:27AM +0800, Chun-Kuang Hu wrote:
> > > From: CK Hu
> > >
> > > mtk mutex is use
On 28/01/2021 12:23, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> property name must include only lowercase and '-'
>
> Fixes: 91f9c963ce79 ("arm64: dts: mt8183: Add display nodes for MT8183")
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> Reviewed-by: Chun-Kuang Hu
> Revi
On 28/01/2021 12:23, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> mt8183 gamma is different with mt8173
> remove mt8173 compatible name for mt8183 gamma
>
> Fixes: 91f9c963ce79 ("arm64: dts: mt8183: Add display nodes for MT8183")
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
On 21/01/2021 01:56, Yongqiang Niu wrote:
> On Wed, 2021-01-20 at 20:38 +0100, Matthias Brugger wrote:
>> On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
>>> move register operation into mmsys path select function
>>
>> Why do you want to do that
Hi Hsin-Yi,
On 29/01/2021 10:22, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> property name must include only lowercase and '-'
>
> Fixes: 91f9c963ce79 ("arm64: dts: mt8183: Add display nodes for MT8183")
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> Reviewed-by: Chun-Kuang
On 30/01/2021 10:45, Chun-Kuang Hu wrote:
> Hi, Matthias:
>
> Chun-Kuang Hu 於 2021年1月10日 週日 上午6:59寫道：
>>
>> Hi, Matthias:
>>
>> Chun-Kuang Hu 於 2020年12月3日 週四 上午7:59寫道：
>>>
>>> rx_callback is a standard mailbox callback mechanism and could
>>> cover the function of proprietary cmdq_task_cb, so
On 29/01/2021 10:22, Hsin-Yi Wang wrote:
> This series is based on kernel/git/chunkuang.hu/linux.git mediatek-drm-next
> The series is tested on a mt8183 krane device.
>
> Change since v12
> - fix mtk_dither_config
>
> Change since v10, v11
> - fix review comments in v9
>
> Change since v9
>
On 08/01/2021 02:48, Yongqiang Niu wrote:
> On Wed, 2020-12-23 at 16:34 +0800, Yongqiang Niu wrote:
>> Add address shift when compose jump instruction
>> to compatible with 35bit format.
>>
>> Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform")
>>
>> Signed-off-by: Yongqi
On 24/12/2020 01:48, Yongqiang Niu wrote:
> Add documentation for the mt8192 gce.
>
> Add gce header file defined the gce hardware event,
> subsys number and constant for mt8192.
>
> Signed-off-by: Yongqiang Niu
> ---
> .../devicetree/bindings/mailbox/mtk-gce.txt| 7 +-
> include/d
On 09/02/2021 16:38, Enric Balletbo Serra wrote:
> Hi Yongqiang Niu,
>
> Thank you for your patch.
>
> Missatge de Yongqiang Niu del dia dt., 5
> de gen. 2021 a les 4:07:
>>
>> the mmsys will more and more complicated after support
>> more and more SoCs, add an independent folder will be
>> m
On 09/02/2021 15:48, Enric Balletbo Serra wrote:
> Hi Hsin-Yi,
>
> Thank you for your patch.
>
> Missatge de Hsin-Yi Wang del dia dv., 29 de gen.
> 2021 a les 10:23:
>>
>> From: Yongqiang Niu
>>
>> Add mtk mutex support for MT8183 SoC.
>>
>> Signed-off-by: Yongqiang Niu
>> Signed-off-by: Hs
Hi Chun-Kuang,
On 20/11/2020 00:46, Chun-Kuang Hu wrote:
Hi, Matthias:
I've provided the example for why of this patch. How do you think
about this patch?
Patch looks good to me. If you want to take it through your tree you can add my
Acked-by: Matthias Brugger
Beware that you might
On 27/11/2020 15:42, Chun-Kuang Hu wrote:
Hi, Matthias:
Matthias Brugger 於 2020年11月27日 週五 下午8:40寫道：
Hi Chun-Kuang,
On 20/11/2020 00:46, Chun-Kuang Hu wrote:
Hi, Matthias:
I've provided the example for why of this patch. How do you think
about this patch?
Patch looks good to m
On 06/10/2020 21:33, Enric Balletbo i Serra wrote:
From: Yongqiang Niu
MMSYS is the driver which controls the routing of these DDP components,
so the definition of the mtk_ddp_comp_id enum should be placed in mtk-mmsys.h
Signed-off-by: Yongqiang Niu
Reviewed-by: Chun-Kuang Hu
Signed-off-b
On 08/03/2022 10:49, Robert Foss wrote:
This reverts commit 32568ae37596b529628ac09b875f4874e614f63f.
Signed-off-by: Robert Foss
Reviewed-by: Chen-Yu Tsai
Reviewed-by: Laurent Pinchart
Acked-by: Matthias Brugger
---
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 2 --
1
the same clocks as
DPI.
Signed-off-by: Markus Schneider-Pargmann
Signed-off-by: Guillaume Ranquet
Reviewed-by: Rob Herring
Reviewed-by: Matthias Brugger
---
.../bindings/display/mediatek/mediatek,dpi.yaml | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git
On 22/02/2022 06:28, Rex-BC Chen wrote:
From: Yongqiang Niu
Add new routing table for MT8186.
In MT8186, there are two routing pipelines for internal and external
display.
Internal display: OVL0->RDMA0->COLOR0->CCORR0->AAL0->GAMMA->POSTMASK0->
DITHER->DSI0
External display
On 22/02/2022 06:28, Rex-BC Chen wrote:
From: Yongqiang Niu
Add MTK mutex support for MT8186 SoC.
We need MTK mutex to control timing of display modules and there
are two display pipelines for MT8186 including internal and external
display.
MTK mutex for internal display:
- Timing source: D
On 01/03/2022 09:01, Rex-BC Chen wrote:
Add "mediatek,mt8186-mmsys" to binding document.
Signed-off-by: Rex-BC Chen
Acked-by: Rob Herring
Applied, thanks!
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Document
On 30/09/2021 17:52, Yongqiang Niu wrote:
Add mtk mutex support for MT8192 SoC.
Signed-off-by: Yongqiang Niu
Signed-off-by: Hsin-Yi Wang
Reviewed-by: CK Hu
Applied to v5.15-next/soc
Thanks!
---
drivers/soc/mediatek/mtk-mutex.c | 35
1 file changed,
On 08/10/2021 04:09, yongqiang.niu wrote:
On Fri, 2021-10-01 at 13:00 +0200, Dafna Hirschfeld wrote:
On 30.09.21 17:52, Yongqiang Niu wrote:
This patch add component POSTMASK.
Signed-off-by: Yongqiang Niu
Signed-off-by: Hsin-Yi Wang
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk
On 08/10/2021 04:05, Yongqiang Niu wrote:
base v5.15
Yongqiang Niu (2):
soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4
soc: mediatek: mmsys: Add mt8192 mmsys routing table
I'm a bit puzzled that you keep on sending this series while I accepted an older
one long time ago:
http
On 30/09/2021 10:31, Enric Balletbo i Serra wrote:
Dear all,
The following patchset is a reimplementation of the patch sent by Jitao
Shi [1] some time ago. As suggested by Chun-Kuang Hu, this time the
reset is done using the reset API, where the mmsys driver is the reset
controller and the mt
: 8f83f26891e1 ("drm/mediatek: Add HDMI support")
Normally there is no new line here.
Cc: Zhiqiang Lin
Cc: CK Hu
Cc: Matthias Brugger
Neither here.
Signed-off-by: Miles Chen
But that are nit-picks. I leave it to the maintainer to decide if he want to fix
that when applying
On 17/01/2022 11:27, AngeloGioacchino Del Regno wrote:
Il 17/01/22 08:04, Yong Wu ha scritto:
MediaTek IOMMU block diagram always like below:
M4U
|
smi-common
|
-
| | ...
| |
larb1 larb2
| |
vdec ven
On 28/01/2022 13:45, Mauro Carvalho Chehab wrote:
Em Fri, 28 Jan 2022 13:40:55 +0100
Mauro Carvalho Chehab escreveu:
Hi Matthias/Yong,
Are you ok if this patch gets merged via the media tree together with the
remaining series, or do you prefer to apply it via SoC tree instead?
Same quest
Hi Mark,
On 02/12/2021 16:11, Mark Yacoub wrote:
From: Mark Yacoub
please make sure to add the linux-mediatek mailinglist in any follow-up
communication.
Regards,
Matthias
[Why]
drm_handle_vblank_events loops over vblank_event_list to send any event
that is current or has passed.
More t
,
+ DDP_COMPONENT_DP_INTF1,
DDP_COMPONENT_DSI0,
DDP_COMPONENT_DSI1,
DDP_COMPONENT_DSI2,
For the mtk-mmsys.h:
Acked-by: Matthias Brugger
On 28/12/2021 10:25, Miles Chen wrote:
Fix unused-but-set variable warning:
drivers/gpu/drm/mediatek/mtk_cec.c:85:6: warning: variable 'tmp' set but not
used [-Wunused-but-set-variable]
Actually we ignore the value passed to mtk_cec_mask. In case of
mtk_cec_mask(cec, CEC_CKGEN, 0 | CEC_32K
On 29/12/2021 04:04, miles.c...@mediatek.com wrote:
Hi,
On 28/12/2021 10:25, Miles Chen wrote:
Fix unused-but-set variable warning:
drivers/gpu/drm/mediatek/mtk_cec.c:85:6: warning: variable 'tmp' set but not
used [-Wunused-but-set-variable]
Actually we ignore the value passed to mtk_ce
gnores the mask. After talking to our hdmi experts, mtk_cec_mask()
should read a register, clean only mask bits, and update (val | mask) bits
to the register.
Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support")
Cc: Zhiqiang Lin
Cc: CK Hu
Cc: Matthias Brugger
Signed-off-by: Miles C
Hi Hans,
On 13/01/2022 11:15, Hans Verkuil wrote:
On 13/01/2022 11:11, AngeloGioacchino Del Regno wrote:
Il 11/01/22 11:57, AngeloGioacchino Del Regno ha scritto:
Il 12/11/21 11:55, Yong Wu ha scritto:
After this patchset, mtk_vcodec_release_enc_pm has only one line.
then remove that function
On 27/04/16 17:05, Philipp Zabel wrote:
> To allow building mediatek-drm.ko as a module, the
> mtk_smi_larb_get and mtk_smi_larb_put symbols have
> to be exported.
>
> Signed-off-by: Philipp Zabel
Signed-off-by: Matthias Brugger
> ---
> drivers/memory/mtk-smi.c | 2 ++
compatible problem?
Frank, did you test with my last series [1]?
Regards,
Matthias
[1] https://patchwork.kernel.org/cover/10686345/
> Regards,
> CK
>
>>
>> regards Frank
>>
>>
>>> Gesendet: Mittwoch, 16. Januar 2019 um 02:39 Uhr
>>> Von: &quo
On 04/01/2019 08:03, chunhui dai wrote:
> DPI sample on rising and falling edge. It can reduce half data io.
>
> Signed-off-by: Jitao Shi
> Signed-off-by: chunhui dai
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 30 ++
> 1 file changed, 30 insertions(+)
>
> diff -
On 04/01/2019 08:03, chunhui dai wrote:
> Recalculate the rate of this clock, by querying hardware.
>
> Signed-off-by: chunhui dai
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi_phy.c| 7 ++--
> drivers/gpu/drm/mediatek/mtk_hdmi_phy.h| 3 +-
> drivers/gpu/drm/mediatek/mtk_mt2701_h
On 04/01/2019 08:03, chunhui dai wrote:
> fix the rate and divder of hdmi phy for MT2701.
This is a bug? Then we would need a fixes tag.
Otherwise you should explain in the commit, that you need to change the
calculation due to previous commits.
Regards,
Matthias
>
> Signed-off-by: chunhui da
On 16/01/2019 08:52, Jitao Shi wrote:
> Use the mtk_pwm_data struction to define different registers
> and add MT8183 specific register operations, such as MT8183
> have commit register, needs to enable double buffer
has_commit is set to false, so I suppose you mean that MT8183 does not have a
c
Hi CK-Hu,
On 01/07/2019 05:55, CK Hu wrote:
> Hi, Matthias:
>
> On Fri, 2018-11-30 at 16:59 +0800, Matthias Brugger wrote:
>>
>> On 30/11/2018 07:43, Stephen Boyd wrote:
>>> Quoting Matthias Brugger (2018-11-21 09:09:52)
>>>>
>>>>
>>&
On 05/07/2019 03:35, CK Hu wrote:
> Hi, Uli:
>
> On Thu, 2019-07-04 at 17:33 +0200, Ulrich Hecht wrote:
>>> On July 4, 2019 at 11:08 AM Matthias Brugger wrote:
>>> You are right, it took far too long for me to respond with a new version of
>>> the
>>&
On 14/03/2019 13:05, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This series are based on 4.20-rc1 and provide 18 patches to
> support mediatek SOC MT8183
> Resend first version
>
I think you send the very same series several times yesterday. Please check your
config and make
On 30/05/2022 22:14, Fabien Parent wrote:
Add MT8365 binding documentation for all the display components that are
compatible with the compatible string from other SoCs.
Signed-off-by: Fabien Parent
Reviewed-by: Matthias Brugger
---
.../bindings/display/mediatek/mediatek,aal.yaml
On 17/06/2022 07:50, CK Hu wrote:
Hi, Fabien:
On Mon, 2022-05-30 at 22:14 +0200, Fabien Parent wrote:
Add mutex support for MT8365 SoC.
Reviewed-by: CK Hu
Applied thanks!
Signed-off-by: Fabien Parent
---
drivers/soc/mediatek/mtk-mutex.c | 40
1 f
On 17/06/2022 07:53, CK Hu wrote:
Hi, Fabien:
On Mon, 2022-05-30 at 22:14 +0200, Fabien Parent wrote:
Right now only the DSI path connections are described in the mt8365
mmsys driver. The external path will be DPI/HDMI. This commit adds
the connections for DPI/HDMI.
Reviewed-by: CK Hu
Hi Hsin-Yi Wang,
On 06/06/2022 17:29, Hsin-Yi Wang wrote:
On Mon, May 30, 2022 at 7:30 PM Hsin-Yi Wang wrote:
krane, kakadu, and kodama boards have a default panel rotation.
Signed-off-by: Hsin-Yi Wang
Reviewed-by: Enric Balletbo i Serra
Tested-by: Enric Balletbo i Serra
---
Hi Matthias
ta-schemas/core.yaml#
+
+title: MediaTek MDP RDMA
+
+maintainers:
+ - Matthias Brugger
I don't think I would be the correct person to maintain this. This should be the
person that is maintaining the driver.
Regards,
Matthias
+
+description: |
+ The mediatek MDP RDMA stands for Read Direc
On 19/04/2022 05:32, Rex-BC Chen wrote:
From: "jason-jh.lin"
In the SoC before, such as mt8173, it has 2 pipelines binding to one
mmsys with the same clock driver and the same power domain.
In mt8195, there are 4 pipelines binding to 4 different mmsys, such as
vdosys0, vdosys1, vppsys0 and
On 19/04/2022 05:32, Rex-BC Chen wrote:
From: "jason-jh.lin"
Power:
1. Add description for power-domains property.
GCE:
1. Add description for mboxes property.
2. Add description for mediatek,gce-client-reg property.
Signed-off-by: jason-jh.lin
Reviewed-by: AngeloGioacchino Del Regno
Re
On 16/04/2022 04:07, Nancy.Lin wrote:
MT8195 vdosys1 has more than 32 reset bits and a different reset base
than other chips. Modify mmsys for support 64 bit and different reset
base.
Signed-off-by: Nancy.Lin
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/soc/mediatek/mt8195-mmsys.h
On 16/04/2022 04:07, Nancy.Lin wrote:
Add cmdq support for mtk-mmsys config API.
The mmsys config register settings need to take effect with the other
HW settings(like OVL_ADAPTOR...) at the same vblanking time.
If we use CPU to write the mmsys reg, we can't guarantee all the
settings can be
On 16/04/2022 04:07, Nancy.Lin wrote:
Add merge start/stop API for cmdq support. The ovl_adaptor merges
are configured with each drm plane update. Need to enable/disable
merge with cmdq making sure all the settings taken effect in the
same vblank.
Signed-off-by: Nancy.Lin
Reviewed-by: Chun-K
On 19/04/2022 11:41, jason-jh.lin wrote:
1. Add mt8195 mmsys compatible for 2 vdosys.
2. Add io_start into each driver data of mt8195 vdosys.
3. Add get match data function to identify mmsys by io_start.
4. Add mt8195 routing table settings of vdosys0.
Signed-off-by: jason-jh.lin
Reviewed-by
On 19/04/2022 11:41, jason-jh.lin wrote:
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin
Acked-by: AngeloGioacchino Del Regno
Tested-by: Fei Shao
Applied thanks!
Matthias
---
drivers/soc/mediatek/mtk-mutex.c | 87 ++--
1 file change
On 22/04/2022 04:32, Jason-JH Lin wrote:
Hi CK,
Thanks for the reviews.
On Thu, 2022-04-21 at 14:50 +0800, CK Hu wrote:
Hi, Jason:
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin
Acked-by: AngeloGioacchino Del
On 19/04/2022 11:41, jason-jh.lin wrote:
The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
But its header need to keep DDP_COMPONENT_DITHER enum
On 19/04/2022 11:41, jason-jh.lin wrote:
After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
Signed-off-by: jason-jh.lin
Reviewed-by: AngeloGioacchino Del Regno
Acked-by: Matthias Brugger
Chun-Kuang, I think
On 11/04/2022 05:58, Rex-BC Chen wrote:
The driver data of MT8183 and MT8173 are different.
The value of has_gamma for MT8173 is true while the value of MT8183 is
false. Therefore, the compatible of disp_aal for MT8183 is not suitable
for the compatible for MT8173.
Signed-off-by: Rex-BC Chen
On 25/04/2022 15:32, Chun-Kuang Hu wrote:
Hi, Matthias:
Matthias Brugger 於 2022年4月22日 週五 下午7:48寫道：
On 16/04/2022 04:07, Nancy.Lin wrote:
Add merge start/stop API for cmdq support. The ovl_adaptor merges
are configured with each drm plane update. Need to enable/disable
merge with cmdq
On 19/08/2022 08:10, Nancy.Lin wrote:
Add mmsys for support 64 reset bits. It is a preparation for MT8195
vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset bits.
1. Add the number of reset bits in mmsys private data
2. move the whole "reset register code section" behind the
"get mmsys->
On 23/08/2022 13:30, Nancy.Lin wrote:
Hi Matthias,
Thanks for the review.
On Tue, 2022-08-23 at 12:20 +0200, Matthias Brugger wrote:
On 19/08/2022 08:10, Nancy.Lin wrote:
Add mmsys for support 64 reset bits. It is a preparation for MT8195
vdosys1 HW reset. MT8195 vdosys1 has more than 32
On 24/08/2022 04:44, Nancy.Lin wrote:
Hi Matthias,
Thanks for your comment.
On Tue, 2022-08-23 at 14:08 +0200, Matthias Brugger wrote:
On 23/08/2022 13:30, Nancy.Lin wrote:
Hi Matthias,
Thanks for the review.
On Tue, 2022-08-23 at 12:20 +0200, Matthias Brugger wrote:
On 19/08/2022 08
again:
Reviewed-by: Matthias Brugger
---
v1 -> v2
Add all the mailinglists that get_maintainers.pl give.
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_dr
Hi Chun-Kuang,
On 02/05/2022 00:54, Chun-Kuang Hu wrote:
Hi, Matthias:
Matthias Brugger 於 2022年4月22日 週五 下午8:42寫道：
On 19/04/2022 11:41, jason-jh.lin wrote:
After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
mmsys header can remove the useless DDP_COMPONENT_DITHER enum
On 15/05/2022 00:45, Chun-Kuang Hu wrote:
Hi, Matthias:
Matthias Brugger 於 2022年5月13日 週五 下午3:42寫道：
Hi Chun-Kuang,
On 02/05/2022 00:54, Chun-Kuang Hu wrote:
Hi, Matthias:
Matthias Brugger 於 2022年4月22日 週五 下午8:42寫道：
On 19/04/2022 11:41, jason-jh.lin wrote:
After mmsys and drm change
On Mon, 2022-05-23 at 12:47 +0200, Guillaume Ranquet wrote:
> Signed-off-by: Guillaume Ranquet
>
We need a commit message here.
> ---
> include/drm/drm_edid.h | 12 +---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
On 01/07/2022 05:15, xinlei@mediatek.com wrote:
From: Xinlei Lee
Add mmsys func to manipulate dpi output format config for MT8186.
Signed-off-by: Jitao Shi
Signed-off-by: Xinlei Lee
---
drivers/soc/mediatek/mt8186-mmsys.h| 1 +
drivers/soc/mediatek/mtk-mmsys.c | 8 +++
On 17/06/2022 16:25, Hsin-Yi Wang wrote:
On Fri, Jun 17, 2022 at 10:10 PM Matthias Brugger
wrote:
Hi Hsin-Yi Wang,
On 06/06/2022 17:29, Hsin-Yi Wang wrote:
On Mon, May 30, 2022 at 7:30 PM Hsin-Yi Wang wrote:
krane, kakadu, and kodama boards have a default panel rotation.
Signed-off
On 22/06/2022 15:08, Nancy.Lin wrote:
Add mtk_mmsys_update_bits API. Simplify code for update mmsys reg.
It is a preparation for adding support for mmsys config API.
Signed-off-by: Nancy.Lin
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: CK Hu
Tested-by: AngeloGioacchino Del Regno
On 22/06/2022 15:08, Nancy.Lin wrote:
Add mmsys for support 64 reset bits. It is a preparation for MT8195
vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset bits.
1. Add the number of reset bits in mmsys private data
2. move the whole "reset register code section" behind the
"get mmsys->
On 23/08/2022 22:17, Nícolas F. R. A. Prado wrote:
On Tue, Aug 23, 2022 at 02:38:22PM +0800, xinlei@mediatek.com wrote:
From: Xinlei Lee
Add mmsys function to manipulate dpi output format configuration for MT8186.
Co-developed-by: Jitao Shi
Signed-off-by: Jitao Shi
Signed-off-by: Xin
r for
mediatek-drm")
Co-developed-by: Yongqiang Niu
Signed-off-by: Yongqiang Niu
Signed-off-by: Allen-KH Cheng
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_
On 14/09/2022 20:23, Jason-JH.Lin wrote:
In mt8195, vdosys0 and vdosys1 are 2 different function blocks
for mediatek-drm, so using 2 compatible instead of identifying
multiple mmsys by io_start.
Fixes: b804923b7ccb ("soc: mediatek: add mtk-mmsys support for mt8195 vdosys0")
Signed-off-by: Jas
On 14/09/2022 20:23, Jason-JH.Lin wrote:
The compatible properties of mt8195 have changed to mediatek,mt8195-vdosys0
and mediatek,mt8195-vdosys1 from mediatek,mt895-mmsys, so remove the unused
compatible.
Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC
binding")
Signe
On 14/09/2022 20:23, Jason-JH.Lin wrote:
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2
On 15/09/2022 09:50, Bo-Chen Chen wrote:
Some definitions in mtk_dp_reg.h are not used, so remove these
redundant codes.
Signed-off-by: Bo-Chen Chen
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_dp_reg.h | 6 --
1 file changed, 6 deletions(-)
diff --git a
0x%x, p1: 0x%x, ret: 0x%lx-0x%lx\n",
| ~^
||
|unsigned int
| %lx
To fix this issue, we use %s to replace 0x%x.
Reported-by: Chun-Kuang Hu
Signed-off-by: Bo-Che
On 14/09/2022 20:23, Jason-JH.Lin wrote:
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2
On 14/09/2022 15:21, xinlei@mediatek.com wrote:
From: Xinlei Lee
Add mmsys func to manipulate dpi output format config for MT8186.
Co-developed-by: Jitao Shi
Signed-off-by: Jitao Shi
Signed-off-by: Xinlei Lee
Reviewed-by: Nís F. R. A. Prado
Applied, thanks!
---
drivers/soc/me
Hi Jason,
On 15/09/2022 03:24, Jason-JH Lin wrote:
Hi Matthias,
Thanks for the reviews.
On Wed, 2022-09-14 at 23:24 +0200, Matthias Brugger wrote:
On 14/09/2022 20:23, Jason-JH.Lin wrote:
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with
On 15/09/2022 18:18, Jason-JH.Lin wrote:
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2
On 31/10/2019 05:17, Hsin-Yi Wang wrote:
> On Fri, Nov 16, 2018 at 12:54 PM wrote:
>>
>> From: Matthias Brugger
>>
>> Switch probing for the MMSYS to support invocation to a
>> plain paltform device. The driver will be probed by the DRM subsystem.
>
On 07/10/2019 10:22, Ulrich Hecht wrote:
> From: Jitao Shi
>
> This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
>
> Signed-off-by: Jitao Shi
> Reviewed-by: Daniel Kurtz
> Reviewed-by: Enric Balletbo i Serra
> [uli: followed API changes, removed FW update feature]
> Sign
Hi CK,
On 07/01/2020 03:56, CK Hu wrote:
> Hi, Dave, Daniel, Matthias:
>
> In mediatek-drm-next-5.6 [1], I've cherry-pick 3 patches from
> v5.5-next/soc [2] because some drm patches depend on these cmdq patches.
> So these cmdq patches exist in both tree now. I want to know how to
> process this
On 08/01/2020 12:14, Matthias Brugger wrote:
> Hi CK,
>
> On 07/01/2020 03:56, CK Hu wrote:
>> Hi, Dave, Daniel, Matthias:
>>
>> In mediatek-drm-next-5.6 [1], I've cherry-pick 3 patches from
>> v5.5-next/soc [2] because some drm patches depend on these cmdq p
Hi Uli,
On 04/10/2019 21:09, Ulrich Hecht wrote:
> Hi!
>
> This driver seems to have fallen by the wayside because, while otherwise
> fine, it has a firmware update feature that requires a blob that is not in
> the linux-firmware repo.[1]
>
> Whatever the cause for that may be, the update code i
emoved FW update feature]
> Signed-off-by: Ulrich Hecht
Now it works, thanks for pushing this forward :)
Tested-by: Matthias Brugger
> ---
>
> Changes since v19:
> - fixed return value of ps8640_probe() when no panel is found
>
> Changes since v18:
> - followed DRM A
Now that the CMA helpers support setting
> DMA_ATTR_NO_KERNEL_MAPPING as needed or not, convert Mediatek driver to
> use CMA helpers.
>
> Cc: CK Hu
> Cc: Philipp Zabel
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: Matthias Brugger
> Cc: linux-arm-ker...@lists.infradead.
On 07/02/2020 06:26, Nicolas Boichat wrote:
> It is useful to know which component cannot be powered on.
>
> Signed-off-by: Nicolas Boichat
> Reviewed-by: Steven Price
> Reviewed-by: Alyssa Rosenzweig
Reviewed-by: Matthias Brugger
> ---
>
> Was useful when try
On 09/12/2019 06:12, CK Hu wrote:
> Hi, Matthias:
>
> On Sat, 2019-12-07 at 23:47 +0100, matthias@kernel.org wrote:
>> From: Matthias Brugger
>>
>> The MediaTek DRM has a block called mmsys, which sets
>> the routing and enalbes the different blocks.
&g
On 09/12/2019 10:39, Enric Balletbo i Serra wrote:
> Hi Matthias,
>
> On 7/12/19 23:47, matthias@kernel.org wrote:
>> From: Matthias Brugger
>>
>> It can happen that the mmsys clock drivers aren't probed before the
>> platform driver gets invoke
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