On 2016-02-24 11:28, Philipp Zabel wrote:
> Am Dienstag, den 23.02.2016, 15:30 -0800 schrieb Stefan Agner:
>> Any comments on this?
>
> None other that I'm all in favor. consider patch 2
> Acked-by: Philipp Zabel
>
Same here!
Acked-by: Manfred Schlaegl
regards
Manfred
On 2015-11-25 18:22, Philipp Zabel wrote:
> Am Mittwoch, den 15.07.2015, 17:50 +0200 schrieb Manfred Schlaegl:
>> To get full support for parallel and LVDS displays with drm:
>> Add representation for clock and data enable polarity in drm_display_mode
>> flags (similar to HSYN
Hello!
These patches address a problem we ran into using parallel displays
with Freescale i.MX53 and i.MX6 SoC's.
In short: We wanted to change the clock signal polarity by using
display-timing in the devicetree description, but the output signal stayed
unchanged.
Parallel displays may have diffe
videomode,
but there was no representation for this in struct drm_display_mode.
Example on Freescale i.MX53/i.MX6 SoC's:
* A parallel display using different clock polarity is set up using
display-timing in devicetree
* ipuv3 parallel outputs clock with wrong polarity
Signed-off-by: Ma
now
de-active unset 1 1
de-active = 0 1 0 <--- corrected
de-active = 1 1 1
Tested on Freescale i.MX53(parallel) and i.MX6(LVDS).
Signed-off-by: Manfred Schlaegl
---
drivers/gpu/drm/imx/ipuv3-crtc.c | 2 --
drivers/gp
