enabled, we need
to disable dmc, since dcf only base on one vop vblank time, so the
other panel will flicker when do ddr frequency scaling.
Signed-off-by: Lin Huang
---
Changes in v5:
- improve some nits
Changes in v4:
- register notifier to devfreq_register_notifier
- use DEVFREQ_PRECHANGE and
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (8):
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: ro
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang
---
Changes in v5:
- delete unuse mux_flag
- use div_flag to distinguish sip
Signed-off-by: Lin Huang
---
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang
---
Changes in v5:
- fit for the ddr type
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- remove clk_ddrc_dpll_src from critical clock list
Changes in v1:
- remove
This patch adds the documentation for rockchip dfi devfreq-event driver.
Signed-off-by: Lin Huang
---
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
.../bindings/devfreq/event/rockchip-dfi.txt | 20
1
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang
Acked-by: Chanwoo Choi
---
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
drivers
This patch adds the documentation for rockchip rk3399 dmc driver.
Signed-off-by: Lin Huang
---
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
.../devicetree/bindings/devfreq/rk3399_dmc.txt | 35 ++
1 file
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang
---
Changes in v5:
- improve dmc driver suggest by Chanwoo Choi
Changes in v4:
- use arm_smccc_smc() function talk to bl31
- delete rockchip_dmc.c
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang
---
Changes in v6:
- none
Changes in v5:
- delete unuse mux_flag
- use
Signed-off-by: Lin Huang
---
Changes in v6:
-None
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang
---
Changes in v6:
- None
Changes in v5:
- fit for the ddr type
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- remove clk_ddrc_dpll_src from critical clock list
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang
Reviewed-by: Chanwoo Choi
---
Changes in v6:
- fix some nit suggest by Chanwoo Choi
Changes in v5:
- improve dmc driver suggest by Chanwoo Choi
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (8):
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: ro
This patch adds the documentation for rockchip dfi devfreq-event driver.
Signed-off-by: Lin Huang
---
Changes in v6:
-None
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
.../bindings/devfreq/event/rockchip-dfi.txt | 20
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang
Acked-by: Chanwoo Choi
---
Changes in v6:
-None
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1
This patch adds the documentation for rockchip rk3399 dmc driver.
Signed-off-by: Lin Huang
---
Changes in v6:
-Add more detail in Documentation
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
.../devicetree/bindings/devfreq
enabled, we need
to disable dmc, since dcf only base on one vop vblank time, so the
other panel will flicker when do ddr frequency scaling.
Signed-off-by: Lin Huang
Reviewed-by: Chanwoo Choi
---
Changes in v6:
- fix a build error
Changes in v5:
- improve some nits
Changes in v4:
- register
Signed-off-by: Lin Huang
---
Changes in v7:
-None
Changes in v6:
-None
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang
---
Changes in v7:
- change SCLK_DDRC name from clk_ddrc to sclk_ddrc
Changes in v6:
- None
Changes in v5:
- fit for the ddr type
Changes in v4:
- None
Changes in v3:
- None
This patch adds the documentation for rockchip dfi devfreq-event driver.
Signed-off-by: Lin Huang
---
Changes in v7:
-None
Changes in v6:
-None
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
.../bindings/devfreq/event/rockchip
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (8):
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: ro
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang
---
Changes in v7:
- add rockchip_ddrclk_sip_ops so we can distinguish other
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang
Acked-by: Chanwoo Choi
---
Changes in v7:
-access need to *4 to get right DDR loading
Changes in v6:
-None
Changes in v5:
-None
Changes in v4:
-None
This patch adds the documentation for rockchip rk3399 dmc driver.
Signed-off-by: Lin Huang
---
Changes in v7:
-None
Changes in v6:
-Add more detail in Documentation
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
-None
Changes in v1:
-None
.../devicetree
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang
Reviewed-by: Chanwoo Choi
---
Changes in v7:
- remove a blank line
Changes in v6:
- fix some nit suggest by Chanwoo Choi
Changes in v5:
- improve
frequency scaling.
Signed-off-by: Lin Huang
Reviewed-by: Chanwoo Choi
---
Changes in v7:
- None
Changes in v6:
- fix a build error
Changes in v5:
- improve some nits
Changes in v4:
- register notifier to devfreq_register_notifier
- use DEVFREQ_PRECHANGE and DEVFREQ_POSTCHANGE to get dmc
This patch adds the documentation for rockchip rk3399 dmc driver.
Signed-off-by: Lin Huang
---
Changes in v8:
- add ddr timing properties
Changes in v7:
-None
Changes in v6:
-Add more detail in Documentation
Changes in v5:
-None
Changes in v4:
-None
Changes in v3:
-None
Changes in v2
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (5):
Documentation: bindings: add dt documentation for dfi controller
PM / devfreq: event: support rockchip dfi cont
This patch adds the documentation for rockchip dfi devfreq-event driver.
Signed-off-by: Lin Huang
---
Changes in v8:
- delete a unuse blank line
Changes in v7:
- None
Changes in v6:
- None
Changes in v5:
- None
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None
Changes in
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang
Signed-off-by: MyungJoo Ham
Acked-by: Chanwoo Choi
---
Changes in v8:
-None
Changes in v7:
-access need to *4 to get right DDR loading
Changes in v6
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang
Signed-off-by: MyngJoo Ham
Reviewed-by: Chanwoo Choi
---
Changes in v8:
- do not use ddr_timing node, get ddr timing directly
Changes in v7
frequency scaling.
Signed-off-by: Lin Huang
Reviewed-by: Chanwoo Choi
---
Changes in v8:
- None
Changes in v7:
- None
Changes in v6:
- fix a build error
Changes in v5:
- improve some nits
Changes in v4:
- register notifier to devfreq_register_notifier
- use DEVFREQ_PRECHANGE and
This patch adds the documentation for rockchip dfi devfreq-event driver.
Signed-off-by: Lin Huang
---
Changes in v8:
- delete a unuse blank line
Changes in v7:
- None
Changes in v6:
- None
Changes in v5:
- None
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None
Changes in
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang
Signed-off-by: MyngJoo Ham
Reviewed-by: Chanwoo Choi
---
Changes in v8:
- None
Changes in v8:
- do not use ddr_timing node, get ddr timing
This patch adds the documentation for rockchip rk3399 dmc driver.
Signed-off-by: Lin Huang
Reviewed-by: Chanwoo Choi
---
Changes in v10:
- add rockchip prefix in property describe
Changes in v9:
- add ddr timing property to node
Changes in v8:
- add ddr timing properties
Changes in v7
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (5):
Documentation: bindings: add dt documentation for dfi controller
PM / devfreq: event: support rockchip dfi cont
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (5):
Documentation: bindings: add dt documentation for dfi controller
PM / devfreq: event: support rockchip dfi cont
This patch adds the documentation for rockchip dfi devfreq-event driver.
Signed-off-by: Lin Huang
---
Changes in v9:
- reorder compatible and reg
Changes in v8:
- delete a unuse blank line
Changes in v7:
- None
Changes in v6:
- None
Changes in v5:
- None
Changes in v4:
- None
Changes in v3
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang
Signed-off-by: MyungJoo Ham
Acked-by: Chanwoo Choi
---
Changes in v9:
-None
Changes in v8:
-None
Changes in v7:
-access need to *4 to get right DDR
frequency scaling.
Signed-off-by: Lin Huang
Reviewed-by: Chanwoo Choi
---
Changes in v9:
- None
Changes in v8:
- None
Changes in v7:
- None
Changes in v6:
- fix a build error
Changes in v5:
- improve some nits
Changes in v4:
- register notifier to devfreq_register_notifier
- use
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (5):
Documentation: bindings: add dt documentation for dfi controller
PM / devfreq: event: support rockchip dfi cont
This patch adds the documentation for rockchip dfi devfreq-event driver.
Signed-off-by: Lin Huang
Acked-by: Chanwoo Choi
---
Changes in v10:
- None
Changes in v9:
- reorder compatible and reg
Changes in v8:
- delete a unuse blank line
Changes in v7:
- None
Changes in v6:
- None
Changes in
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang
Signed-off-by: MyungJoo Ham
Acked-by: Chanwoo Choi
---
Changes in v10:
-None
Changes in v9:
-None
Changes in v8:
-None
Changes in v7:
-access need
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang
Signed-off-by: MyngJoo Ham
Reviewed-by: Chanwoo Choi
---
Changes in v10:
- None
Changes in v9:
- None
Changes in v8:
- None
Changes in v8:
- do
frequency scaling.
Signed-off-by: Lin Huang
Reviewed-by: Chanwoo Choi
---
Changes in v10:
- None
Changes in v9:
- None
Changes in v8:
- None
Changes in v7:
- None
Changes in v6:
- fix a build error
Changes in v5:
- improve some nits
Changes in v4:
- register notifier to
This patch adds the documentation for rockchip rk3399 dmc driver.
Signed-off-by: Lin Huang
---
Changes in v9:
- add ddr timing property to node
Changes in v8:
- add ddr timing properties
Changes in v7:
- None
Changes in v6:
-Add more detail in Documentation
Changes in v5:
-None
Changes in
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (4):
rockchip: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add ddrc clock support
PM / d
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang
---
drivers/clk/rockchip/clk-rk3399.c | 16
include/dt-bindings/clock/rk3399-cru.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/drivers/clk/rockchip
there is dfi controller on rk3399 platform, it can monitor
ddr load, register this controller to devfreq framework, and
default to use simple_ondeamnd policy, and do ddr frequency
scaling base on this result.
Signed-off-by: Lin Huang
---
drivers/devfreq/Kconfig | 2 +-
drivers
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang
---
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-ddr.c
when in ddr frequency scaling process, vop can not do
enable or disable operate, since dcf will base on vop vblank
time to do frequency scaling and need to get vop irq if there
have vop enabled. So need register to dmc notifier, and we can
get the dmc status.
Signed-off-by: Lin Huang
Signed-off-by: Lin Huang
---
Changes in v1:
- None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
index 50a44cf..8a0f0442 100644
--- a/include/dt-bindings/clock/rk3399
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang
---
Changes in v1:
- move dfi controller to event, Suggestion by Chanwoo Choi
- fix set voltage sequence when set rate fail
- change Kconfig type
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (6):
rockchip: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang
---
Changes in v1:
- NOne
drivers/devfreq/event/Kconfig| 7 +
drivers/devfreq/event/Makefile | 1 +
drivers/devfreq/event/rockchip
when in ddr frequency scaling process, vop can not do
enable or disable operate, since dcf will base on vop vblank
time to do frequency scaling and need to get vop irq if there
have vop enabled. So need register to dmc notifier, and we can
get the dmc status.
Signed-off-by: Lin Huang
---
Changes
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang
---
Changes in v1:
- None
drivers/clk/rockchip/Makefile | 1 +
drivers
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang
---
Changes in v1:
- remove ddrc source CLK_IGNORE_UNUSED flag, Suggestion by Doug
- move clk_ddrc and clk_ddrc_dpll_src to critical, Suggestion by Doug
drivers/clk/rockchip/clk
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (6):
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: ro
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang
---
Changes in v2:
- use GENMASK instead val_mask
- use divider_recalc_rate
Signed-off-by: Lin Huang
---
Changes in v2:
- None
Changes in v1:
- None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
index 50a44cf..8a0f0442 100644
--- a/include/dt
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang
---
Changes in v2:
- remove clk_ddrc_dpll_src from critical clock list
Changes in v1:
- remove ddrc source CLK_IGNORE_UNUSED flag
- move clk_ddrc and clk_ddrc_dpll_src to critical
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang
Acked-by: Chanwoo Choi
---
Changes in v2:
- use clk_disable_unprepare and clk_enable_prepare
- remove clk_enable_prepare in probe
- remove
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang
---
Changes in v2:
- None
Changes in v1:
- move dfi controller to event
- fix set voltage sequence when set rate fail
- change Kconfig type from
when in ddr frequency scaling process, vop can not do
enable or disable operate, since dcf will base on vop vblank
time to do frequency scaling and need to get vop irq if there
have vop enabled. So need register to dmc notifier, and we can
get the dmc status.
Signed-off-by: Lin Huang
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (6):
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: ro
From: Shengfei xu
This patch adds support for the SiP interface, we can pass dram
paramtert to bl31, and control ddr frequency scaling in bl31.
Signed-off-by: Shengfei xu
Signed-off-by: Lin Huang
---
Changes in v3:
- None
Changes in v2:
- None
Changes in v1:
- None
drivers/firmware
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang
---
Changes in v3:
- use sip call to set/read ddr rate
Changes in v2:
- use
Signed-off-by: Lin Huang
---
Changes in v3:
-None
Changes in v2:
- None
Changes in v1:
- None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
index 50a44cf..8a0f0442
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang
---
Changes in v3:
- None
Changes in v2:
- remove clk_ddrc_dpll_src from critical clock list
Changes in v1:
- remove ddrc source CLK_IGNORE_UNUSED flag
- move clk_ddrc and
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang
Acked-by: Chanwoo Choi
---
Changes in v3:
- None
Changes in v2:
- use clk_disable_unprepare and clk_enable_prepare
- remove clk_enable_prepare in probe
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang
---
Changes in v3:
- operate dram setting through sip call
- imporve set rate flow
Changes in v2:
- None
Changes in v1:
- move dfi controller to
when in ddr frequency scaling process, vop can not do
enable or disable operate, since dcf will base on vop vblank
time to do frequency scaling and need to get vop irq if there
have vop enabled. So need register to dmc notifier, and we can
get the dmc status.
Signed-off-by: Lin Huang
---
Changes
low
| |
| |
wait dcf interrupt<---trigger dcf interrupt
|
|
return
Lin Huang (6):
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: ro
From: Heiko Stübner
add clock flag parameter so we can pass specific clock flag
(like CLK_GET_RATE_NOCACHE etc..)to pll driver.
Signed-off-by: Heiko Stübner
Signed-off-by: Lin Huang
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- None
Changes in v1:
- None
drivers/clk
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang
---
Changes in v4:
- use arm_smccc_smc() to set/read ddr rate
Changes in v3
Signed-off-by: Lin Huang
---
Changes in v4:
-None
Changes in v3:
-None
Changes in v2:
- None
Changes in v1:
- None
include/dt-bindings/clock/rk3399-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
index
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- remove clk_ddrc_dpll_src from critical clock list
Changes in v1:
- remove ddrc source CLK_IGNORE_UNUSED flag
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Signed-off-by: Lin Huang
Acked-by: Chanwoo Choi
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- use clk_disable_unprepare and clk_enable_prepare
- remove
base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Signed-off-by: Lin Huang
---
Changes in v4:
- use arm_smccc_smc() function talk to bl31
- delete rockchip_dmc.c file and config
- delete dmc_notify
- adjust probe order
enabled, we need
to disable dmc, since dcf only base on one vop vblank time, so the
other panel will flicker when do ddr frequency scaling.
Signed-off-by: Lin Huang
---
Changes in v4:
- register notifier to devfreq_register_notifier
- use DEVFREQ_PRECHANGE and DEVFREQ_POSTCHANGE to get dmc status
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
Changes in v2:
- update patch following Enric suggest
Changes
If want to do training outside DP Firmware, need phy voltage swing
and pre_emphasis value.
Signed-off-by: Lin Huang
---
Changes in v2:
- None
Changes in v3:
- modify property description and add this property to Example
Changes in v4:
- None
Changes in v5:
- None
Changes in v6:
- change
we may use rockchip_phy_typec struct in other driver, so split
it to separate header.
Signed-off-by: Lin Huang
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
Changes in v5:
- None
Changes in v6:
- new patch here
drivers/phy/rockchip/phy-rockchip-typec.c | 47
fallback if sw training fails.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
Reviewed-by: Sean Paul
---
Changes in v2:
- update patch following Enric suggest
Changes in v3:
- use variable fw_training instead sw_training_success
- base on DP SPCE, if training fail use lower link rate to retry
From: Chris Zhong
We may support training outside firmware, so we need support
dpcd read/write to get the message or do some setting with
display.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
Reviewed-by: Sean Paul
Reviewed-by: Enric Balletbo
---
Changes in v2:
- update patch
We use jitter bypass mode for spdif, so do not need to set jitter mode
related bit in SPDIF_CTRL_ADDR register. Also, we need to enable
SPDIF_ENABLE bit.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
drivers/gpu/drm/rockchip/cdn-dp-reg.c | 16 +---
1 file changed, 1
some monitors care about the parity bit in the sub-frame of I2S,
but the cdn-dp always set this bit to "1", so these monitors
do not have sound output if use i2s, use spdif can fix this issue.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
sound/soc/rockchip/rk3399_gru_so
we may use rockchip_phy_typec struct in other driver, so split
it to separate header.
Signed-off-by: Lin Huang
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
Changes in v5:
- None
Changes in v6:
- new patch here
Changes in v7:
- move new element to next patch
drivers/phy
From: Chris Zhong
We may support training outside firmware, so we need support
dpcd read/write to get the message or do some setting with
display.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
Reviewed-by: Sean Paul
Reviewed-by: Enric Balletbo
---
Changes in v2:
- update patch
If want to do training outside DP Firmware, need phy voltage swing
and pre_emphasis value.
Signed-off-by: Lin Huang
Reviewed-by: Rob Herring
---
Changes in v2:
- None
Changes in v3:
- modify property description and add this property to Example
Changes in v4:
- None
Changes in v5:
- None
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
Changes in v2:
- update patch following Enric suggest
Changes
fallback if sw training fails.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
Reviewed-by: Sean Paul
---
Changes in v2:
- update patch following Enric suggest
Changes in v3:
- use variable fw_training instead sw_training_success
- base on DP SPCE, if training fail use lower link rate to retry
If want to do training outside DP Firmware, need phy voltage swing
and pre_emphasis value.
Signed-off-by: Lin Huang
---
Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/phy
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
drivers/phy/rockchip/phy-rockchip-typec.c | 286
.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
drivers/gpu/drm/rockchip/Makefile | 3 +-
drivers/gpu/drm/rockchip/cdn-dp-core.c | 23 +-
drivers/gpu/drm/rockchip/cdn-dp-core.h | 2 +
drivers/gpu/drm/rockchip/cdn-dp-link-training.c | 398
From: Chris Zhong
We may support training outside firmware, so we need support
dpcd read/write to get the message or do some setting with
display.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
drivers/gpu/drm/rockchip/cdn-dp-core.c | 55
drivers/gpu/drm
If want to do training outside DP Firmware, need phy voltage swing
and pre_emphasis value.
Signed-off-by: Lin Huang
---
Changes in v2:
- rebase
Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Signed-off-by: Chris Zhong
Signed-off-by: Lin Huang
---
Changes in v2:
- update patch following Enric suggest
drivers
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