Re: [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Add compute engine ABI

2022-04-27 Thread Kumar Valsan, Prathap
On Mon, Apr 25, 2022 at 11:41:36AM +0100, Tvrtko Ursulin wrote: > > On 22/04/2022 20:50, Matt Roper wrote: > > We're now ready to start exposing compute engines to userspace. > > > > While we're at it, let's extend the kerneldoc description for the other > > engine types as well. > > > > Cc: Dan

Re: [PATCH v2 2/4] drm/i915/xehp: Add register for compute engine's MMIO-based TLB invalidation

2022-04-28 Thread Kumar Valsan, Prathap
On Wed, Apr 27, 2022 at 09:19:24PM -0700, Matt Roper wrote: > Compute engines have a separate register that the driver should use to > perform MMIO-based TLB invalidation. > > Note that the term "context" in this register's bspec description is > used to refer to the engine instance (in the same w

Re: [PATCH 10/11] drm/i915/pvc: skip all copy engines from aux table invalidate

2022-05-02 Thread Kumar Valsan, Prathap
On Mon, May 02, 2022 at 09:34:16AM -0700, Matt Roper wrote: > From: Lucas De Marchi > > As we have more copy engines now, mask all of them from aux table > invalidate. > > Cc: Prathap Kumar Valsan > Signed-off-by: Lucas De Marchi > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/gt/ge

Re: [Intel-gfx] [PATCH] drm/i915: Split GAM and MSLICE steering

2022-09-21 Thread Kumar Valsan, Prathap
On Fri, Sep 16, 2022 at 07:53:40AM -0700, Matt Roper wrote: > On Fri, Sep 16, 2022 at 10:02:32AM +0100, Tvrtko Ursulin wrote: > > > > On 16/09/2022 02:43, Matt Roper wrote: > > > Although the bspec lists several MMIO ranges as "MSLICE," it turns out > > > that a subset of these are of a "GAM" subc

Re: [Intel-gfx] [PATCH] drm/i915: Split GAM and MSLICE steering

2022-09-21 Thread Kumar Valsan, Prathap
On Wed, Sep 21, 2022 at 12:26:17PM -0700, Matt Roper wrote: > On Wed, Sep 21, 2022 at 12:58:08PM -0400, Kumar Valsan, Prathap wrote: > > On Fri, Sep 16, 2022 at 07:53:40AM -0700, Matt Roper wrote: > > > On Fri, Sep 16, 2022 at 10:02:32AM +0100, Tvrtko Ursulin wrote: > > &g